Patents by Inventor Ramachandran Muralidhar

Ramachandran Muralidhar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11954615
    Abstract: A method of improving at least one of quality and yield of a physical process comprises: obtaining values, from respective performances of the physical process, for a plurality of variables associated with the physical process; determining at least one Gaussian mixture model (GMM) representing the values for the variables for the performances of the physical process; based at least in part on the at least one GMM, computing at least one anomaly score for at least one of the variables for at least one of the performances of the physical process; based on the at least one anomaly score, identifying the at least one of the performances of the physical process as an outlier; and, based at least in part on the outlier identification, modifying the at least one of the variables for one or more subsequent performances of the physical process.
    Type: Grant
    Filed: October 16, 2019
    Date of Patent: April 9, 2024
    Assignee: International Business Machines Corporation
    Inventors: Dung Tien Phan, Robert Jeffrey Baseman, Fateh Ali Tipu, Nam H. Nguyen, Ramachandran Muralidhar
  • Patent number: 11428699
    Abstract: A sensor including a surface plasmon resonance detector with a reservoir for containing a liquid sample. The sensor further includes a sensing metallic film positioned within the reservoir so that at least a majority of a surface of the sensing metallic film is to be in contact with the liquid sample being housed within the reservoir. The sensory also includes a semiconductor device having a contact in electrical communication with the sensing metal containing film that is positioned within the reservoir. The semiconductor device measures the net charges of molecules within the liquid sample within a Debye length from the sensing metallic film.
    Type: Grant
    Filed: April 30, 2019
    Date of Patent: August 30, 2022
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Bobby E. Feller, Jianqiang Lin, Robert D. Miller, Ramachandran Muralidhar, Tak H. Ning, Sufi Zafar
  • Patent number: 11422139
    Abstract: A sensor including a surface plasmon resonance detector with a reservoir for containing a liquid sample. The sensor further includes a sensing metallic film positioned within the reservoir so that at least a majority of a surface of the sensing metallic film is to be in contact with the liquid sample being housed within the reservoir. The sensory also includes a semiconductor device having a contact in electrical communication with the sensing metal containing film that is positioned within the reservoir. The semiconductor device measures the net charges of molecules within the liquid sample within a Debye length from the sensing metallic film.
    Type: Grant
    Filed: April 30, 2019
    Date of Patent: August 23, 2022
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Bobby E. Feller, Jianqiang Lin, Robert D. Miller, Ramachandran Muralidhar, Tak H. Ning, Sufi Zafar
  • Patent number: 11410891
    Abstract: Anomaly detection and remedial recommendation techniques for improving the quality and yield of microelectronic products are provided. In one aspect, a method for quality and yield improvement via anomaly detection includes: collecting time series sensor data during individual steps of a semiconductor manufacturing process; calculating anomaly scores for each of the individual steps using a predictive model; and implementing changes to the semiconductor manufacturing process based on the anomaly scores. A system for quality and yield improvement via anomaly detection is also provided.
    Type: Grant
    Filed: August 26, 2019
    Date of Patent: August 9, 2022
    Assignee: International Business Machines Corporation
    Inventors: Dzung Phan, Robert Baseman, Nam H. Nguyen, Fateh Tipu, Ramachandran Muralidhar
  • Patent number: 11216595
    Abstract: A private key of a public-private key pair with a corresponding identity is written to an integrated circuit including a processor, a non-volatile memory, and a cryptographic engine coupled to the processor and the non-volatile memory. The private key is written to the non-volatile memory. The integrated circuit is implemented in complementary metal-oxide semiconductor 14 nm or smaller technology. The integrated circuit is permanently modified, subsequent to the writing, such that further writing to the non-volatile memory is disabled and such that the private key can be read only by the cryptographic engine and not off-chip. Corresponding integrated circuits and wafers are also disclosed.
    Type: Grant
    Filed: September 21, 2019
    Date of Patent: January 4, 2022
    Assignee: International Business Machines Corporation
    Inventors: Richard H. Boivie, Eduard A. Cartier, Daniel J. Friedman, Kohji Hosokawa, Charanjit Jutla, Wanki Kim, Chandrasekara Kothandaraman, Chung Lam, Frank R. Libsch, Seiji Munetoh, Ramachandran Muralidhar, Vijay Narayanan, Dirk Pfeiffer, Devendra K. Sadana, Ghavam G. Shahidi, Robert L. Wisnieff
  • Patent number: 11162929
    Abstract: A method for measuring pollution that includes providing a plurality of analyte sensors arranged in a grid over a sensing area, wherein the analyte sensors measure a pollutant, and positioning at least one current sensor in the sensing area. A pollution source is localized using a pollution source locator including a dispersion model and at least one hardware processor to interpolate a location of a pollution source from variations in current measured from the current sensors and measurements of pollutants from the analyte sensors.
    Type: Grant
    Filed: September 18, 2019
    Date of Patent: November 2, 2021
    Assignee: International Business Machines Corporation
    Inventors: Josephine B. Chang, Hendrik F. Hamann, Siyuan Lu, Ramachandran Muralidhar, Theodore G. Van Kessel
  • Patent number: 11158793
    Abstract: Cross bar arrays and a method for forming cross-bar arrays are provided. The cross bar array device includes first conductive lines spaced apart and extending in a first direction in a first plane, the first conductive lines including a bottom electrode layer. Second conductive lines are spaced apart and arranged transversely to the first conductive lines in a second plane, the second conductive lines including a top electrode layer. An oxide layer formed on the bottom electrode layer of the first conductive lines and in contact with the top electrode layer of the second conductive lines such that a resistive element is formed through the oxide layer at intersection points between the first conductive lines and the second conductive lines. A multivalent oxide spacer that switches between at least two oxidative states on at least one sidewall of the oxide layer between the first plane and the second plane.
    Type: Grant
    Filed: March 28, 2019
    Date of Patent: October 26, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Takashi Ando, Ramachandran Muralidhar
  • Patent number: 11107835
    Abstract: A method is presented for incorporating a metal-ferroelectric-metal (MFM) structure in a cross-bar array in back end of the line (BEOL) processing. The method includes forming a first electrode, forming a ferroelectric layer in direct contact with the first electrode, forming a second electrode in direct contact with the ferroelectric layer, such that the first electrode and the ferroelectric layer are perpendicular to the second electrode to form the cross-bar array, and biasing the second electrode to adjust domain wall movement within the ferroelectric layer.
    Type: Grant
    Filed: October 30, 2019
    Date of Patent: August 31, 2021
    Assignee: International Business Machines Corporation
    Inventors: Jin Ping Han, Ramachandran Muralidhar, Paul M. Solomon, Dennis M. Newns, Martin M. Frank
  • Patent number: 11094820
    Abstract: A method of fabricating a symmetric element of a resistive processing unit (RPU) includes forming a substrate with a channel region connecting two doped regions, and forming a source above one of the two doped regions and a drain above the other of the two doped regions. A gate is formed above the channel region, and a bar ferroelectric is disposed above the channel region and below the gate.
    Type: Grant
    Filed: April 13, 2020
    Date of Patent: August 17, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jin-Ping Han, Ramachandran Muralidhar, Dennis M. Newns, Paul M. Solomon
  • Patent number: 11079366
    Abstract: Embodiments of the invention are directed to an integrated sensing system that includes a movable orientation device configured to dynamically position the movable orientation device based on receiving an air-flow. A gas sensor is coupled to the movable orientation device. The gas sensor includes a recognition element configured to detect a chemical in a plume. The movable orientation device is configured to perform a synchronized sensing operation that includes, based at least in part on the movable orientation device receiving the air-flow, moving the movable orientation device to dynamically maintain a predetermined orientation of the movable orientation device relative to a direction of the air-flow. The predetermined orientation includes positioning the gas sensor in a path of the air-flow, wherein the air-flow is influencing the plume to move along the path such that the recognition element is exposed to the plume.
    Type: Grant
    Filed: March 16, 2018
    Date of Patent: August 3, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Levente Klein, Theodore van Kessel, Ramachandran Muralidhar, Michael A. Schappert
  • Patent number: 10997321
    Abstract: A private key of a public-private key pair with a corresponding identity is written to an integrated circuit including a processor, a non-volatile memory, and a cryptographic engine coupled to the processor and the non-volatile memory. The private key is written to the non-volatile memory. The integrated circuit is implemented in complementary metal-oxide semiconductor 14 nm or smaller technology. The integrated circuit is permanently modified, subsequent to the writing, such that further writing to the non-volatile memory is disabled and such that the private key can be read only by the cryptographic engine and not off-chip. Corresponding integrated circuits and wafers are also disclosed.
    Type: Grant
    Filed: September 21, 2019
    Date of Patent: May 4, 2021
    Assignee: International Business Machines Corporation
    Inventors: Richard H. Boivie, Eduard A. Cartier, Daniel J. Friedman, Kohji Hosokawa, Charanjit Jutla, Wanki Kim, Chandrasekara Kothandaraman, Chung Lam, Frank R. Libsch, Seiji Munetoh, Ramachandran Muralidhar, Vijay Narayanan, Dirk Pfeiffer, Devendra K. Sadana, Ghavam G. Shahidi, Robert L. Wisnieff
  • Publication number: 20210117836
    Abstract: A method of improving at least one of quality and yield of a physical process comprises: obtaining values, from respective performances of the physical process, for a plurality of variables associated with the physical process; determining at least one Gaussian mixture model (GMM) representing the values for the variables for the performances of the physical process; based at least in part on the at least one GMM, computing at least one anomaly score for at least one of the variables for at least one of the performances of the physical process; based on the at least one anomaly score, identifying the at least one of the performances of the physical process as an outlier; and, based at least in part on the outlier identification, modifying the at least one of the variables for one or more subsequent performances of the physical process.
    Type: Application
    Filed: October 16, 2019
    Publication date: April 22, 2021
    Inventors: Dung Tien Phan, Robert Jeffrey Baseman, Fateh Ali Tipu, Nam H. Nguyen, Ramachandran Muralidhar
  • Publication number: 20210103221
    Abstract: A method for process control using predictive long short term memory includes obtaining historical post-process measurements taken on prior products of the manufacturing process; obtaining historical in-process measurements taken on prior workpieces during the manufacturing process; training a neural network to predict each of the historical post-process measurements, in response to the corresponding historical in-process measurements and preceding historical post-process measurements; obtaining present in-process measurements on a present workpiece during the manufacturing process; predicting a future post-process measurement for the present workpiece, by providing the present in-process measurements and the historical post-process measurements as inputs to the neural network; and adjusting at least one controllable variable of the manufacturing process in response to the prediction of the future post-process measurement.
    Type: Application
    Filed: October 8, 2019
    Publication date: April 8, 2021
    Inventors: Dung Tien Phan, Robert J. Baseman, Ramachandran Muralidhar, Fateh A. Tipu, Nam H. Nguyen
  • Publication number: 20210066141
    Abstract: Anomaly detection and remedial recommendation techniques for improving the quality and yield of microelectronic products are provided. In one aspect, a method for quality and yield improvement via anomaly detection includes: collecting time series sensor data during individual steps of a semiconductor manufacturing process; calculating anomaly scores for each of the individual steps using a predictive model; and implementing changes to the semiconductor manufacturing process based on the anomaly scores. A system for quality and yield improvement via anomaly detection is also provided.
    Type: Application
    Filed: August 26, 2019
    Publication date: March 4, 2021
    Inventors: Dzung Phan, Robert Baseman, Nam H. Nguyen, Fateh Tipu, Ramachandran Muralidhar
  • Patent number: 10903424
    Abstract: A method is presented for enabling heat dissipation in resistive random access memory (RRAM) devices. The method includes forming a plurality of conductive lines within an interlayer dielectric (ILD) and forming a RRAM stack over a conductive line of the plurality of conductive lines, the RRAM stack including a bottom electrode, a conductive pillar, thermal conducting layers, and a top electrode. The thermal conducting layers are disposed on opposed ends of the conductive pillar. The thermal conducting layers directly contact the top electrode and the bottom electrode. The thermal conducting layers include aluminum oxide (Al2O3).
    Type: Grant
    Filed: May 7, 2019
    Date of Patent: January 26, 2021
    Assignee: International Business Machines Corporation
    Inventors: Praneet Adusumilli, Takashi Ando, Jianshi Tang, Ramachandran Muralidhar
  • Publication number: 20200357989
    Abstract: A method is presented for enabling heat dissipation in resistive random access memory (RRAM) devices. The method includes forming a plurality of conductive lines within an interlayer dielectric (ILD) and forming a RRAM stack over a conductive line of the plurality of conductive lines, the RRAM stack including a bottom electrode, a conductive pillar, thermal conducting layers, and a top electrode. The thermal conducting layers are disposed on opposed ends of the conductive pillar. The thermal conducting layers directly contact the top electrode and the bottom electrode. The thermal conducting layers include aluminum oxide (Al2O3).
    Type: Application
    Filed: May 7, 2019
    Publication date: November 12, 2020
    Inventors: Praneet Adusumilli, Takashi Ando, Jianshi Tang, Ramachandran Muralidhar
  • Publication number: 20200313088
    Abstract: Cross bar arrays and a method for forming cross-bar arrays are provided. The cross bar array device includes first conductive lines spaced apart and extending in a first direction in a first plane, the first conductive lines including a bottom electrode layer. Second conductive lines are spaced apart and arranged transversely to the first conductive lines in a second plane, the second conductive lines including a top electrode layer. An oxide layer formed on the bottom electrode layer of the first conductive lines and in contact with the top electrode layer of the second conductive lines such that a resistive element is formed through the oxide layer at intersection points between the first conductive lines and the second conductive lines. A multivalent oxide spacer that switches between at least two oxidative states on at least one sidewall of the oxide layer between the first plane and the second plane.
    Type: Application
    Filed: March 28, 2019
    Publication date: October 1, 2020
    Inventors: Takashi Ando, Ramachandran Muralidhar
  • Patent number: 10775258
    Abstract: Heuristic-based techniques for gas leak source identification are provided. In one aspect, a method for identifying a location of a gas leak source includes: obtaining gas sensor data and wind data synchronously from a gas leak detection system having a network of interconnected motes comprising gas sensors and wind sensors, with the gas sensors arranged around possible gas leak sources in a given area of interest; identifying the location of the gas leak source using the gas sensor data and wind data; and determining a magnitude of gas leak from the gas leak source using the location of the gas leak source and a distance d between the location of the gas leak source and a select one of the gas sensors from which the gas sensor data was obtained. A gas leak detection system is also provided.
    Type: Grant
    Filed: March 13, 2018
    Date of Patent: September 15, 2020
    Assignee: International Business Machines Corporation
    Inventors: Ramachandran Muralidhar, Josephine B. Chang, Siyuan Lu, Theodore van Kessel, Hendrik F. Hamann
  • Publication number: 20200243688
    Abstract: A method of fabricating a symmetric element of a resistive processing unit (RPU) includes forming a substrate with a channel region connecting two doped regions, and forming a source above one of the two doped regions and a drain above the other of the two doped regions. A gate is formed above the channel region, and a bar ferroelectric is disposed above the channel region and below the gate.
    Type: Application
    Filed: April 13, 2020
    Publication date: July 30, 2020
    Inventors: Jin-Ping Han, Ramachandran Muralidhar, Dennis M. Newns, Paul M. Solomon
  • Patent number: 10680105
    Abstract: A method of fabricating a symmetric element of a resistive processing unit (RPU) includes forming a substrate with a channel region connecting two doped regions, and forming a source above one of the two doped regions and a drain above the other of the two doped regions. A gate is formed above the channel region, and a bar ferroelectric is disposed above the channel region and below the gate.
    Type: Grant
    Filed: March 21, 2017
    Date of Patent: June 9, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jin-Ping Han, Ramachandran Muralidhar, Dennis M. Newns, Paul M. Solomon