Patents by Inventor Ramachandran Muralidhar

Ramachandran Muralidhar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • GATE STRUCTURES AND METHODS OF MANUFACTURE
    Publication number: 20130119473
    Abstract: A metal gate structure with a channel material and methods of manufacture such structure is provided. The method includes forming dummy gate structures on a substrate. The method further includes forming sidewall structures on sidewalls of the dummy gate structures. The method further includes removing the dummy gate structures to form a first trench and a second trench, defined by the sidewall structures. The method further includes forming a channel material on the substrate in the first trench and in the second trench. The method further includes removing the channel material from the second trench while the first trench is masked. The method further includes filling remaining portions of the first trench and the second trench with gate material.
    Type: Application
    Filed: November 10, 2011
    Publication date: May 16, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Unoh Kwon, Ramachandran Muralidhar, Viorel Ontalus
  • Nanocluster charge storage device
    Patent number: 8373221
    Abstract: An integrated circuit and method of forming an integrated circuit having a memory portion minimizes an amount of oxidation of nanocluster storage elements in the memory portion. A first region of the integrated circuit has non-memory devices, each having a control electrode or gate formed of a single conductive layer of material. A second region of the integrated circuit has a plurality of memory cells, each having a control electrode of at least two conductive layers of material that are positioned one overlying another. The at least two conductive layers are at substantially a same electrical potential when operational and form a single gate electrode. In one form each memory cell gate has two polysilicon layers overlying a nanocluster storage layer.
    Type: Grant
    Filed: December 26, 2007
    Date of Patent: February 12, 2013
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Robert F. Steimle, Ramachandran Muralidhar, Bruce E. White
  • FABRICATION OF FIELD-EFFECT TRANSISTORS WITH ATOMIC LAYER DOPING
    Publication number: 20130032865
    Abstract: Field effect transistors fabricated using atomic layer doping processes are disclosed. In accordance with an embodiment of an atomic layer doping method, a semiconducting surface and a dopant gas mixture are prepared. Further, a dopant layer is grown on the semiconducting surface by applying the dopant gas mixture to the semiconducting surface under a pressure that is less than 500 Torr and a temperature that is between 300° C. and 750° C. The dopant layer includes at least 4×1020 active dopant atoms per cm3 that react with atoms on the semiconducting surface such that the reacted atoms increase the conductivity of the semiconducting surface.
    Type: Application
    Filed: September 7, 2012
    Publication date: February 7, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kevin K. Chan, Young-Hee Kim, Isaac Lauer, Ramachandran Muralidhar, Dae-Gyu Park, Xinhui Wang, Min Yang
  • FABRICATION OF FIELD-EFFECT TRANSISTORS WITH ATOMIC LAYER DOPING
    Publication number: 20130032883
    Abstract: Field effect transistors fabricated using atomic layer doping processes are disclosed. In accordance with an embodiment of an atomic layer doping method, a semiconducting surface and a dopant gas mixture are prepared. Further, a dopant layer is grown on the semiconducting surface by applying the dopant gas mixture to the semiconducting surface under a pressure that is less than 500 Torr and a temperature that is between 300° C. and 750° C. The dopant layer includes at least 4×1020 active dopant atoms per cm3 that react with atoms on the semiconducting surface such that the reacted atoms increase the conductivity of the semiconducting surface.
    Type: Application
    Filed: August 4, 2011
    Publication date: February 7, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kevin K. Chan, Young-Hee Kim, Isaac Lauer, Ramachandran Muralidhar, Dae-Gyu Park, Xinhui Wang, Min Yang
  • Stressed channel FET with source/drain buffers
    Patent number: 8361847
    Abstract: A method for forming a stressed channel field effect transistor (FET) with source/drain buffers includes etching cavities in a substrate on either side of a gate stack located on the substrate; depositing source/drain buffer material in the cavities; etching the source/drain buffer material to form vertical source/drain buffers adjacent to a channel region of the FET; and depositing source/drain stressor material in the cavities adjacent to and over the vertical source/drain buffers.
    Type: Grant
    Filed: January 19, 2011
    Date of Patent: January 29, 2013
    Assignee: International Business Machines Corporation
    Inventors: Jeffrey B. Johnson, Ramachandran Muralidhar, Philip J. Oldiges, Viorel C. Ontalus, Kai Xiu
  • Method to optimize work function in complementary metal oxide semiconductor (CMOS) structures
    Patent number: 8354313
    Abstract: In one embodiment, the method for forming a complementary metal oxide semiconductor (CMOS) device includes providing a semiconductor substrate including a first device region and a second device region. An n-type conductivity semiconductor device is formed in one of the first device region or the second device region using a gate structure first process, in which the n-type conductivity semiconductor device includes a gate structure having an n-type work function metal layer. A p-type conductivity semiconductor device is formed in the other of the first device region or the second device region using a gate structure last process, in which the p-type conductivity semiconductor device includes a gate structure including a p-type work function metal layer.
    Type: Grant
    Filed: April 30, 2010
    Date of Patent: January 15, 2013
    Assignee: International Business Machines Corporation
    Inventors: Unoh Kwon, Dechao Guo, Siddarth A. Krishnan, Ramachandran Muralidhar
  • Semiconductor device with high K dielectric control terminal spacer structure
    Patent number: 8349684
    Abstract: A semiconductor device including a control terminal sidewall spacer structure made of a high-K dielectric material. The semiconductor device includes a control terminal where the spacer structure is a sidewall spacer structure for the control terminal. The semiconductor device includes current terminal regions located in a substrate. In some examples, the spacer structure has a height that is less than the height of the control terminal. In some examples, the spacer structure includes portions located over the regions of the substrate between the first current terminal region and the second current terminal region.
    Type: Grant
    Filed: November 19, 2009
    Date of Patent: January 8, 2013
    Assignees: Freescale Semiconductor, Inc., International Business Machines Corporation
    Inventors: Jin Cai, Amlan Majumdar, Ramachandran Muralidhar, Ghavam G. Shahidi
  • WIRING SWITCH DESIGNS BASED ON A FIELD EFFECT DEVICE FOR RECONFIGURABLE INTERCONNECT PATHS
    Publication number: 20120306017
    Abstract: An integrated circuit, including a substrate, at least one metal wiring layer disposed above the substrate. The metal wiring layer including a wiring switch and a plurality of patterned conductors. The wiring switch including a back gate field effect transistor (BGFET).
    Type: Application
    Filed: May 24, 2012
    Publication date: December 6, 2012
    Applicant: International Business Machines Corporation
    Inventors: Daniel C. Edelstein, Stephen M. Gates, Ramachandran Muralidhar, Thomas N. Theis
  • Field Effect Transistor Device with Self-Aligned Junction and Spacer
    Publication number: 20120286360
    Abstract: A field effect transistor device includes a substrate including a source region, a drain region, and a channel region disposed between the source region and the drain region, wherein the source region is connected to the channel region with a source extension portion, and the drain region is connected to the channel region with a drain extension portion, a first spacer portion disposed on the source region, the drain region and a first portion of the source extension portion, and a first portion of the drain extension portion, a second spacer portion disposed on a second portion of the source extension portion, and a second portion of the drain extension portion, a gate stack portion disposed on the channel region.
    Type: Application
    Filed: July 24, 2012
    Publication date: November 15, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Dechao Guo, Pranita Kulkarni, Ramachandran Muralidhar, Chun-Chen Yeh
  • Field Effect Transistor Device With Self-Aligned Junction
    Publication number: 20120286371
    Abstract: A field effect transistor device includes a substrate including a source region, a drain region, and a channel region disposed between the source region and the drain region, wherein the source region is connected to the channel region with a source extension portion, and the drain region is connected to the channel region with a drain extension portion, wherein the channel region includes a source transition portion including n-type and p-type ions and a drain transition portion including n-type and p-type ions, and a gate stack portion disposed on the channel region.
    Type: Application
    Filed: July 26, 2012
    Publication date: November 15, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Dechao Guo, Pranita Kulkarni, Ramachandran Muralidhar, Chun-Chen Yeh
  • MINIMIZING LEAKAGE CURRENT AND JUNCTION CAPACITANCE IN CMOS TRANSISTORS BY UTILIZING DIELECTRIC SPACERS
    Publication number: 20120261672
    Abstract: A semiconductor structure and method for forming dielectric spacers and epitaxial layers for a complementary metal-oxide-semiconductor field effect transistor (CMOS transistor) are disclosed. Specifically, the structure and method involves forming dielectric spacers that are disposed in trenches and are adjacent to the silicon substrate, which minimizes leakage current. Furthermore, epitaxial layers are deposited to form source and drain regions, wherein the source region and drain regions are spaced at a distance from each other. The epitaxial layers are disposed adjacent to the dielectric spacers and the transistor body regions (i.e., portion of substrate below the gates), which can minimize transistor junction capacitance. Minimizing transistor junction capacitance can enhance the switching speed of the CMOS transistor.
    Type: Application
    Filed: April 12, 2011
    Publication date: October 18, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Dureseti Chidambarrao, Ramachandran Muralidhar, Philip J. Oldiges, Viorel Ontalus
  • STRESSED CHANNEL FET WITH SOURCE/DRAIN BUFFERS
    Publication number: 20120181549
    Abstract: A method for forming a stressed channel field effect transistor (FET) with source/drain buffers includes etching cavities in a substrate on either side of a gate stack located on the substrate; depositing source/drain buffer material in the cavities; etching the source/drain buffer material to form vertical source/drain buffers adjacent to a channel region of the FET; and depositing source/drain stressor material in the cavities adjacent to and over the vertical source/drain buffers.
    Type: Application
    Filed: January 19, 2011
    Publication date: July 19, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jeffrey B. Johnson, Ramachandran Muralidhar, Philip J. Oldiges, Viorel Ontalus, Kai Xiu
  • Field Effect Transistor Device With Self-Aligned Junction
    Publication number: 20120038007
    Abstract: A method for fabricating a field effect transistor device includes forming a dummy gate stack on a first portion of a substrate, forming a source region and a drain region adjacent to the dummy gate stack, forming a ion doped source extension portion in the substrate, the source extension portion extending from the source region into the first portion of the substrate, forming an ion doped drain extension portion in the substrate, the drain extension portion extending from the drain region into the first portion of the substrate, removing a portion of the dummy gate stack to expose an interfacial layer of the dummy gate stack, implanting ions in the source extension portion and the drain extension portion to form a channel region in the first portion of the substrate, removing the interfacial layer, and forming a gate stack on the channel region of the substrate.
    Type: Application
    Filed: August 16, 2010
    Publication date: February 16, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Dechao Guo, Pranita Kulkarni, Ramachandran Muralidhar, Chun-Chen Yeh
  • Field Effect Transistor Device with Self-Aligned Junction and Spacer
    Publication number: 20120038008
    Abstract: In one aspect of the present invention, a method for fabricating a field effect transistor device includes forming a dummy gate stack on a first portion of a substrate, forming a source region and a drain region adjacent to the dummy gate stack, forming a ion doped source extension portion in the substrate, forming an ion doped drain extension portion in the substrate, forming a first spacer portion adjacent to the dummy gate stack, removing the dummy gate stack to expose a channel region of the substrate, a portion of the ion doped source extension portion, and a portion of the ion doped drain extension portion, forming a second spacer portion on the exposed portion of the ion doped source extension portion and on the exposed portion of the ion doped drain extension portion, and forming a gate stack on the exposed channel region of the substrate.
    Type: Application
    Filed: August 16, 2010
    Publication date: February 16, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Dechao Guo, Pranita Kulkarni, Ramachandran Muralidhar, Chun-Chen Yeh
  • Phase change memory structures
    Patent number: 8097873
    Abstract: A phase change memory cell has a first electrode, a plurality of pillars, and a second electrode. The plurality of pillars are electrically coupled with the first electrode. Each of the pillars comprises a phase change material portion and a heater material portion. The second electrode is electrically coupled to each of the pillars. In some examples, the pillars have a width less than 20 nanometers.
    Type: Grant
    Filed: September 14, 2010
    Date of Patent: January 17, 2012
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Ramachandran Muralidhar, Tushar P. Merchant, Rajesh A. Rao
  • PHASE CHANGE MEMORY CELL WITH HEATER AND METHOD THEREFOR
    Publication number: 20120007031
    Abstract: A method for forming a phase change memory cell (PCM) includes forming a heater for the phase change memory and forming a phase change structrure electrically coupled to the heater. The forming a heater includes siliciding a material including silicon to form a silicide structure, wherein the heater includes at least a portion of the silicide structure. The phase change structure exhibits a first resistive value when in a first phase state and exhibits a second resistive value when in a second phase state. The silicide structure produces heat when current flows through the silicide structure for changing the phase state of the phase change structure.
    Type: Application
    Filed: September 21, 2011
    Publication date: January 12, 2012
    Applicant: FREESCALE SEMICONDUCTOR, INC.
    Inventors: LEO MATHEW, DHARMESH JAWARANI, TUSHAR P. MERCHANT, RAMACHANDRAN MURALIDHAR
  • METHOD TO OPTIMIZE WORK FUNCTION IN COMPLEMENTARY METAL OXIDE SEMICONDUCTOR (CMOS) STRUCTURES
    Publication number: 20110269276
    Abstract: In one embodiment, the method for forming a complementary metal oxide semiconductor (CMOS) device includes providing a semiconductor substrate including a first device region and a second device region. An n-type conductivity semiconductor device is formed in one of the first device region or the second device region using a gate structure first process, in which the n-type conductivity semiconductor device includes a gate structure having an n-type work function metal layer. A p-type conductivity semiconductor device is formed in the other of the first device region or the second device region using a gate structure last process, in which the p-type conductivity semiconductor device includes a gate structure including a p-type work function metal layer.
    Type: Application
    Filed: April 30, 2010
    Publication date: November 3, 2011
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Unoh Kwon, Dechao Guo, Siddarth A. Krishnan, Ramachandran Muralidhar
  • Phase change memory cell with heater and method therefor
    Patent number: 8043888
    Abstract: A method for forming a phase change memory cell (PCM) includes forming a heater for the phase change memory and forming a phase change structure electrically coupled to the heater. The forming a heater includes siliciding a material including silicon to form a silicide structure, wherein the heater includes at least a portion of the silicide structure. The phase change structure exhibits a first resistive value when in a first phase state and exhibits a second resistive value when in a second phase state. The silicide structure produces heat when current flows through the silicide structure for changing the phase state of the phase change structure.
    Type: Grant
    Filed: January 18, 2008
    Date of Patent: October 25, 2011
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Leo Mathew, Dharmesh Jawarani, Tushar P. Merchant, Ramachandran Muralidhar
  • FinFET formation with a thermal oxide spacer hard mask formed from crystalline silicon layer
    Patent number: 7947589
    Abstract: A semiconductor process and apparatus provide a FinFET device by forming a second single crystal semiconductor layer (19) that is isolated from an underlying first single crystal semiconductor layer (17) by a buried insulator layer (18); patterning and etching the second single crystal semiconductor layer (19) to form a single crystal mandrel (42) having vertical sidewalls; thermally oxidizing the vertical sidewalls of the single crystal mandrel to grow oxide spacers (52) having a substantially uniform thickness; selectively removing any remaining portion of the single crystal mandrel (42) while substantially retaining the oxide spacers (52); and selectively etching the first single crystal semiconductor layer (17) using the oxide spacers (52) to form one or more FinFET channel regions (92).
    Type: Grant
    Filed: September 2, 2009
    Date of Patent: May 24, 2011
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Ramachandran Muralidhar, Marwan H. Khater
  • SEMICONDUCTOR DEVICE WITH HIGH K DIELECTRIC CONTROL TERMINAL SPACER STRUCTURE
    Publication number: 20110117712
    Abstract: A semiconductor device including a control terminal sidewall spacer structure made of a high-K dielectric material. The semiconductor device includes a control terminal where the spacer structure is a sidewall spacer structure for the control terminal. The semiconductor device includes current terminal regions located in a substrate. In some examples, the spacer structure has a height that is less than the height of the control terminal. In some examples, the spacer structure includes portions located over the regions of the substrate between the first current terminal region and the second current terminal region.
    Type: Application
    Filed: November 19, 2009
    Publication date: May 19, 2011
    Inventors: RAMACHANDRAN MURALIDHAR, Jin Cai, Amlan Majumdar, Ghavam G. Shahidi