Abstract: In one example of the present technology, an input/output memory management unit (IOMMU) of a computing device is configured to: receive a prefetch message including a virtual address from a central processing unit (CPU) core of a processor of the computing device; perform a page walk on the virtual address through a page table stored in a main memory of the computing device to obtain a prefetched translation of the virtual address to a physical address; and store the prefetched translation of the virtual address to the physical address in a translation lookaside buffer (TLB) of the IOMMU.

Abstract: Embodiments of the present disclosure includes techniques for cache memory replacement in a processing unit. A first data production operation to store first data to a first cache line of the cache memory is detected at a first time. A retention status of the first cache line is updated to a first retention level as a result of the first data production operation. Protection against displacement of the first data in the first cache line is increased based on the first retention level. A first data consumption operation retrieving the first data from the first cache line is detected at a second time after the first time. The retention status of the first cache line is updated to a second retention level as a result of the first data consumption operation, the second retention level being a lower level of retention than the first retention level.

Abstract: Embodiments of the present disclosure includes techniques for partial memory updates in a computer system. A data structure template is received. A first write data of a first write operation is received from a first data source, the first write operation performed in connection with provisioning of a first data payload to memory communicatively coupled with a processing unit. A first merge operation is performed involving the first write data and the first data structure template to obtain a first data structure update. The first data structure update is written to the memory, thereby improving efficiency of updating a first data structure associated with the first data payload.

Abstract: Examples are described herein that relate to a mesh in a switch fabric. The mesh can include one or more buses that permit operations (e.g., read, write, or responses) to continue in the same direction, drop off to a memory, drop off a bus to permit another operation to use the bus, or receive operations that are changing direction. A latency estimate can be determined at least for operations that drop off from a bus to permit another operation to use the bus or receive and channel operations that are changing direction. An operation with a highest latency estimate (e.g., time of traversing a mesh) can be permitted to use the bus, even causing another operation, that is not to change direction, to drop off the bus and re-enter later.

Abstract: A switch or network interface can detect congestion caused by a flow of packets. The switch or network interface can generate a congestion hint packet and send the congestion hint packet directly to a source transmitter of the flow of packets that caused the congestion. The congestion hint packet can include information that the source transmitter can use to determine a remedial action to attempt to alleviate or stop congestion at the switch or network interface. For example, the transmitter can reduce a transmit rate of the flow of packets and/or select another route for the flow of packets. Some or all switches or network interfaces between the source transmitter and a destination endpoint can employ flow differentiation whereby a queue is selected to accommodate for a flow's sensitivity to latency.

Abstract: There is disclosed in one example a computing apparatus, including: a processor; a multilevel cache including a plurality of cache levels; a peripheral device configured to write data directly to a selected cache level; and a cache monitoring circuit, including a cache counter to track cache lines evicted from the selected cache level without being processed; and logic to provide a direct write policy according to the cache counter.

Abstract: Examples are described herein that relate to a mesh in a switch fabric. The mesh can include one or more buses that permit operations (e.g., read, write, or responses) to continue in the same direction, drop off to a memory, drop off a bus to permit another operation to use the bus, or receive operations that are changing direction. A latency estimate can be determined at least for operations that drop off from a bus to permit another operation to use the bus or receive and channel operations that are changing direction. An operation with a highest latency estimate (e.g., time of traversing a mesh) can be permitted to use the bus, even causing another operation, that is not to change direction, to drop off the bus and re-enter later.

Abstract: There is disclosed in one example a computing apparatus, including: a processor; a multilevel cache including a plurality of cache levels; a peripheral device configured to write data directly to a selected cache level; and a cache monitoring circuit, including a cache counter to track cache lines evicted from the selected cache level without being processed; and logic to provide a direct write policy according to the cache counter.

Abstract: There is disclosed in one example a computing apparatus, including: a processor; a multilevel cache including a plurality of cache levels; a peripheral device configured to write data directly to a directly writable cache; and a cache monitoring circuit, including cache counters La to be incremented when a cache line is allocated into the directly writable cache, Lp to be incremented when a cache line is processed by the processor and deallocated from the directly writable cache, and Le to be incremented when a cache line is evicted from the directly writable cache to the memory, wherein the cache monitoring circuit is to determine a direct write policy according to the cache counters.

Abstract: A switch or network interface can detect congestion caused by a flow of packets. The switch or network interface can generate a congestion hint packet and send the congestion hint packet directly to a source transmitter of the flow of packets that caused the congestion. The congestion hint packet can include information that the source transmitter can use to determine a remedial action to attempt to alleviate or stop congestion at the switch or network interface. For example, the transmitter can reduce a transmit rate of the flow of packets and/or select another route for the flow of packets. Some or all switches or network interfaces between the source transmitter and a destination endpoint can employ flow differentiation whereby a queue is selected to accommodate for a flow's sensitivity to latency.

Abstract: There is disclosed in one example a computing apparatus, including: a processor; a multilevel cache including a plurality of cache levels; a peripheral device configured to write data directly to a directly writable cache; and a cache monitoring circuit, including cache counters La to be incremented when a cache line is allocated into the directly writable cache, Lp to be incremented when a cache line is processed by the processor and deallocated from the directly writable cache, and Le to be incremented when a cache line is evicted from the directly writable cache to the memory, wherein the cache monitoring circuit is to determine a direct write policy according to the cache counters.

Abstract: A method of assessing energy efficiency of a High-performance computing (HPC) system, including: selecting a plurality of HPC workloads to run on a system under test (SUT) with one or more power constraints, wherein the SUT includes a plurality of HPC nodes in the HPC system, executing the plurality of HPC workloads on the SUT, and generating a benchmark metric for the SUT based on a baseline configuration for each selected HPC workload and a plurality of measured performance per power values for each executed workload at each selected power constraint is shown.

Abstract: A method of assessing energy efficiency of a High-performance computing (HPC) system, including: selecting a plurality of HPC workloads to run on a system under test (SUT) with one or more power constraints, wherein the SUT includes a plurality of HPC nodes in the HPC system, executing the plurality of HPC workloads on the SUT, and generating a benchmark metric for the SUT based on a baseline configuration for each selected HPC workload and a plurality of measured performance per power values for each executed workload at each selected power constraint is shown.

Abstract: In one embodiment this disclosure provides a network device that includes an input port configured to link to a first device to receive a packet from the first device, wherein the received packet having a first label encoded therein, the value of the first label is specific to the link between the network device and the first device; the input port having an input port identifier, the input port identifier and the first label form an input tuple; a plurality of output ports configured to link to respective ones of a plurality of second devices, each output port having a respective output port identifier; a forwarding table that includes at least one input tuple and a corresponding set of output tuples; wherein each output tuple comprises an output port identifier and a second label, the value of the second label is specific to the link between the network device and a respective one of the second plurality of devices; and routing circuitry configured to compare the input tuple of the received packet with at l

Abstract: In one embodiment this disclosure provides a network device that includes an input port configured to link to a first device to receive a packet from the first device, wherein the received packet having a first label encoded therein, the value of the first label is specific to the link between the network device and the first device; the input port having an input port identifier, the input port identifier and the first label form an input tuple; a plurality of output ports configured to link to respective ones of a plurality of second devices, each output port having a respective output port identifier; a forwarding table that includes at least one input tuple and a corresponding set of output tuples; wherein each output tuple comprises an output port identifier and a second label, the value of the second label is specific to the link between the network device and a respective one of the second plurality of devices; and routing circuitry configured to compare the input tuple of the received packet with at l

Abstract: In an embodiment, an apparatus is provided that may include circuitry to generate, at least in part, and/or receive, at least in part, at least one request to access at least one portion of data. The at least one request may indicate, at least in part, at least one subset of the at least one portion of the data that is of relatively higher importance than one or more other subsets of the at least one portion of the data that are of relatively lower importance. The at least one request may be to request, at least in part, that the at least one subset be accessed prior to the one or more other subsets are accessed. The at least one request may be comprised, at least in part, in at least one packet in accordance with a protocol that permits variable packet size.

Abstract: Methods and apparatus relating to network packet payload compression/decompression are described. In an embodiment, an uncompressed packet payload may be compressed before being transferred between various components of a computing system. For example, a packet payload may be compressed prior to transfer between network interface cards or controllers (NICs) and storage devices (e.g., including a main system memory and/or cache(s)), as well as between processors (or processor cores) and storage devices (e.g., including main system memory and/or caches). Other embodiments are also disclosed.

Abstract: Embodiments of an apparatus, method, and system for encoding direct cache access transactions based on a memory access data structure are disclosed. In one embodiment, an apparatus includes memory access logic and transaction logic. The memory access logic is to determine whether to allow a memory access based on a memory access data structure. The transaction logic is to assign direct cache access attributes to a transaction based on the memory access data structure.

Abstract: In an embodiment, an apparatus is provided that may include circuitry to generate, at least in part, and/or receive, at least in part, at least one request to access at least one portion of data. The at least one request may indicate, at least in part, at least one subset of the at least one portion of the data that is of relatively higher importance than one or more other subsets of the at least one portion of the data that are of relatively lower importance. The at least one request may be to request, at least in part, that the at least one subset be accessed prior to the one or more other subsets are accessed. The at least one request may be comprised, at least in part, in at least one packet in accordance with a protocol that permits variable packet size.

Abstract: Methods and apparatus relating to network packet payload compression/decompression are described. In an embodiment, an uncompressed packet payload may be compressed before being transferred between various components of a computing system. For example, a packet payload may be compressed prior to transfer between network interface cards or controllers (NICs) and storage devices (e.g., including a main system memory and/or cache(s)), as well as between processors (or processor cores) and storage devices (e.g., including main system memory and/or caches). Other embodiments are also disclosed.