Patents by Inventor Ramaprasath Vilangudipitchai
Ramaprasath Vilangudipitchai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11823052Abstract: Certain aspects of the present disclosure are directed to methods and apparatus for configuring a multiply-accumulate (MAC) block in an artificial neural network. A method generally includes receiving, at a neural processing unit comprising one or more logic elements, at least one input associated with a use-case of the neural processing unit; obtaining a set of weights associated with the at least one input; selecting a precision for the set of weights; modifying the set of weights based on the selected precision; and generating an output based, at least in part, on the at least one input, the modified set of weights, and an activation function.Type: GrantFiled: October 11, 2019Date of Patent: November 21, 2023Assignee: QUALCOMM INCORPORATEDInventors: Giby Samson, Srivatsan Chellappa, Ramaprasath Vilangudipitchai, Seung Hyuk Kang
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Publication number: 20230221789Abstract: A system on chip (SOC) comprising: first memory block and a second memory block; a processing unit coupled to the first memory block and the second memory block; a first power multiplexor disposed between the first memory block and the second memory block and coupled to a first power rail configured to provide an operating voltage to both the first memory block and the second memory block; and enable logic circuitry disposed at a periphery of the SOC away from the first memory block and the second memory block, the enable logic being coupled to control terminals of the first power multiplexor.Type: ApplicationFiled: July 28, 2021Publication date: July 13, 2023Inventors: Giby SAMSON, Smeeta HEGGOND, Jitu Khushalbhai MISTRY, Paras GUPTA, Keyurkumar Karsanbhai KANSAGRA, Kamesh MEDISETTI, Ramaprasath VILANGUDIPITCHAI, Arshath SHEEPARAMATTI
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Patent number: 11476186Abstract: A cell on an IC includes a first set of Mx layer interconnects coupled to a first voltage, a second set of Mx layer interconnects coupled to a second voltage different than the first voltage, and a MIM capacitor structure below the Mx layer. The MIM capacitor structure includes a CTM, a CBM, and an insulator between portions of the CTM and the CBM. The first set of Mx layer interconnects is coupled to the CTM. The second set of Mx layer interconnects is coupled to the CBM. The MIM capacitor structure is between the Mx layer and an Mx-1 layer. The MIM capacitor structure includes a plurality of openings. The MIM capacitor structure is continuous within the cell and extends to at least two edges of the cell. In one configuration, the MIM capacitor structure extends to each edge of the cell.Type: GrantFiled: October 27, 2020Date of Patent: October 18, 2022Assignee: QUALCOMM INCORPORATEDInventors: Ramaprasath Vilangudipitchai, Gudoor Reddy, Samrat Sinharoy, Smeeta Heggond, Anil Kumar Koduru, Kamesh Medisetti, Seung Hyuk Kang
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Patent number: 11237580Abstract: A system includes: a first power supply; a second power supply; a headswitch disposed between the first power supply and logic circuitry; an enable driver coupling the second power supply to a control terminal of the headswitch; and a voltage generator operable to adjust a control voltage from the second power supply to the control terminal of the headswitch in response to a first voltage level of the first power supply exceeding a reference voltage level.Type: GrantFiled: September 9, 2020Date of Patent: February 1, 2022Assignee: QUALCOMM INCORPORATEDInventors: Giby Samson, Foua Vang, Ramaprasath Vilangudipitchai, Seung Hyuk Kang, Venugopal Boynapalli
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Publication number: 20210391249Abstract: A cell on an IC includes a first set of Mx layer interconnects coupled to a first voltage, a second set of Mx layer interconnects coupled to a second voltage different than the first voltage, and a MIM capacitor structure below the Mx layer. The MIM capacitor structure includes a CTM, a CBM, and an insulator between portions of the CTM and the CBM. The first set of Mx layer interconnects is coupled to the CTM. The second set of Mx layer interconnects is coupled to the CBM. The MIM capacitor structure is between the Mx layer and an Mx-1 layer. The MIM capacitor structure includes a plurality of openings. The MIM capacitor structure is continuous within the cell and extends to at least two edges of the cell. In one configuration, the MIM capacitor structure extends to each edge of the cell.Type: ApplicationFiled: October 27, 2020Publication date: December 16, 2021Inventors: Ramaprasath VILANGUDIPITCHAI, Gudoor REDDY, Samrat SINHAROY, Smeeta HEGGOND, Anil Kumar KODURU, Kamesh MEDISETTI, Seung Hyuk KANG
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Publication number: 20210110267Abstract: Certain aspects of the present disclosure are directed to methods and apparatus for configuring a multiply-accumulate (MAC) block in an artificial neural network. A method generally includes receiving, at a neural processing unit comprising one or more logic elements, at least one input associated with a use-case of the neural processing unit; obtaining a set of weights associated with the at least one input; selecting a precision for the set of weights; modifying the set of weights based on the selected precision; and generating an output based, at least in part, on the at least one input, the modified set of weights, and an activation function.Type: ApplicationFiled: October 11, 2019Publication date: April 15, 2021Inventors: Giby SAMSON, Srivatsan CHELLAPPA, Ramaprasath VILANGUDIPITCHAI, Seung Hyuk KANG
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Publication number: 20210058076Abstract: A hybrid fin flip flop circuit may comprise a mixture of 1-fin transistors and multi-fin transistors. In one example, a flip flop circuit may comprise 1-fin transistors in at least one of the critical paths of the flip flop circuit such as the drive circuit, the input circuit, or the output circuit. In one example, a flip flop circuit may include: an input circuit; a clock driver circuit; an output circuit; and a latch circuit; wherein one of the input circuit, the clock driver circuit, or the output circuit comprises a multi-fin transistor and the latch circuit comprises a plurality of 1-fin transistors.Type: ApplicationFiled: August 22, 2019Publication date: February 25, 2021Inventors: Andi ZHAO, Ramaprasath VILANGUDIPITCHAI, Hyeokjin LIM, Seung Hyuk KANG
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Publication number: 20200341537Abstract: In certain aspects, a system comprises a power collapsible logic block, a plurality of retention flip-flops coupled to the power collapsible logic blocks, wherein the plurality of retention flip-flops includes a group of master-slave flip-flops and a group of balloon flip-flops, and a power controller configured to retain states of the group of balloon flip-flops and states of the group of master-slave flip-flops in a first sleep state and to retain the states of the group of balloon flip-flops but not states of the group of master-slave flip-flops in a deep sleep state.Type: ApplicationFiled: April 26, 2019Publication date: October 29, 2020Inventors: Giby SAMSON, Ramaprasath VILANGUDIPITCHAI, Seung Hyuk KANG, Eunjoo HWANG, Hai ZHU, Divjyot BHAN
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Patent number: 10505541Abstract: A level shifter according to some embodiments is disclosed. In some embodiments, a level shifter includes a middle-of-the-line (MOL) capacitor; and a circuit including at least one thin-film transistor coupled to the MOL capacitor, wherein an input voltage provided to the MOL capacitor is split between the MOL capacitor and the circuit. The MOL capacitor can be formed with a contact strip adjacent to a gate structure. A method of forming a level shifter using thin-oxide technologies includes forming a middle-of-the-line (MOL) capacitor; forming a circuit with one or more thin-film transistors; and coupling the MOL capacitor to the circuit such that an input voltage provided at the MOL capacitor is split between the MOL capacitor and the circuit.Type: GrantFiled: August 18, 2017Date of Patent: December 10, 2019Assignee: QUALCOMM IncorporatedInventors: Albert Kumar, Ramaprasath Vilangudipitchai, Vasisht Vadi, Paul Penzes
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Patent number: 10459510Abstract: In certain aspects, an apparatus includes a first plurality of power switch devices. Each of the first plurality of power switch devices includes a delay line having a programmable time delay, and a power switch coupled between a supply rail and a circuit block, wherein the power switch has a control input coupled to the delay line. The apparatus also includes a switch manager configured to program the time delays of the delay lines in the first plurality of power switch devices based on a number of active circuit blocks in a system.Type: GrantFiled: January 17, 2019Date of Patent: October 29, 2019Assignee: QUALCOMM IncorporatedInventors: Raghavendra Srinivas, Uday Shankar Mudigonda, Giby Samson, Ramaprasath Vilangudipitchai, Dorav Kumar
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Publication number: 20190058477Abstract: A level shifter according to some embodiments is disclosed. In some embodiments, a level shifter includes a middle-of-the-line (MOL) capacitor; and a circuit including at least one thin-film transistor coupled to the MOL capacitor, wherein an input voltage provided to the MOL capacitor is split between the MOL capacitor and the circuit. The MOL capacitor can be formed with a contact strip adjacent to a gate structure. A method of forming a level shifter using thin-oxide technologies includes forming a middle-of-the-line (MOL) capacitor; forming a circuit with one or more thin-film transistors; and coupling the MOL capacitor to the circuit such that an input voltage provided at the MOL capacitor is split between the MOL capacitor and the circuit.Type: ApplicationFiled: August 18, 2017Publication date: February 21, 2019Inventors: Albert KUMAR, Ramaprasath VILANGUDIPITCHAI, Vasisht VADI, Paul PENZES
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Patent number: 10109619Abstract: In an aspect of the disclosure, a MOS device for reducing routing congestion caused by using split n-well cells in a merged n-well circuit block is provided. The MOS device may include a first set of cells adjacent to each other in a first direction. The MOS device may include a second set of cells adjacent to each other in the first direction and adjacent to the first set of cells in a second direction. The second set of cells each may include a first n-well, a second n-well, and a third n-well separated from each other. The MOS device may include an interconnect extending in the first direction in the second set of cells. The interconnect may provide a voltage source to the first n-well of each of the second set of cells.Type: GrantFiled: June 6, 2016Date of Patent: October 23, 2018Assignee: QUALCOMM IncorporatedInventors: Harshat Pant, Mohammed Yousuff Shariff, Parissa Najdesamii, Ramaprasath Vilangudipitchai, Divjyot Bhan
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Patent number: 10103626Abstract: A power multiplexor includes: a first branch including a first transistor coupled in series with a second transistor between a first power supply and a power output; a second branch including a third transistor coupled in series with a fourth transistor between a second power supply and the power output; a controller configured to selectively assert and de-assert a control signal to the first branch and the second branch; a first voltage level shifter coupled between the second transistor and the controller; and a second voltage level shifter coupled between the third transistor and the controller.Type: GrantFiled: July 12, 2017Date of Patent: October 16, 2018Assignee: QUALCOMM IncorporatedInventors: Venkatasubramanian Narayanan, Dorav Kumar, Ramaprasath Vilangudipitchai, Venugopal Boynapalli
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Publication number: 20180224921Abstract: An integrated circuit (IC) is disclosed with clock glitch prevention for a retention operational mode. In an example aspect, the IC includes a clock signal source that generates a source value for a clock signal, which is distributed by a clock tree along a downstream direction. The IC further includes a deviant clock signal generator, a clock signal controller, and a retention storage device. The deviant clock signal generator is disposed along the clock tree downstream from the clock signal source and generates a deviant value for the clock signal. The clock signal controller prevents downstream propagation of the deviant value of the clock signal responsive to a retention signal. The retention storage device is disposed downstream from the clock signal controller. The retention storage device processes data responsive to the clock signal and retains a data value during a power collapse event responsive to the retention signal.Type: ApplicationFiled: February 6, 2017Publication date: August 9, 2018Inventors: Harshat Pant, Ramaprasath Vilangudipitchai, Srijith Nair, Mohammad Tamjidi
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Patent number: 10026735Abstract: A MOS IC includes pMOS transistors, each having a pMOS transistor drain, source, and gate. Each pMOS transistor gate extends in a first direction and is coupled to other pMOS transistor gates. Each pMOS transistor source/drain are coupled to a first voltage source. The MOS IC further includes a first metal interconnect extending over the pMOS transistors. The first metal interconnect has first and second ends. The first metal interconnect is coupled to each pMOS transistor gate and is coupled to a second voltage source less than the first voltage source. One of each pMOS transistor gate or the second voltage source is coupled to the first metal interconnect through at least one tap point located between the first and second ends. The pMOS transistors and the first metal interconnect function as a decoupling capacitor.Type: GrantFiled: November 23, 2016Date of Patent: July 17, 2018Assignee: QUALCOMM IncorporatedInventors: Andi Zhao, Ramaprasath Vilangudipitchai, Dorav Kumar
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Publication number: 20180145071Abstract: A MOS IC includes pMOS transistors, each having a pMOS transistor drain, source, and gate. Each pMOS transistor gate extends in a first direction and is coupled to other pMOS transistor gates. Each pMOS transistor source/drain are coupled to a first voltage source. The MOS IC further includes a first metal interconnect extending over the pMOS transistors. The first metal interconnect has first and second ends. The first metal interconnect is coupled to each pMOS transistor gate and is coupled to a second voltage source less than the first voltage source. One of each pMOS transistor gate or the second voltage source is coupled to the first metal interconnect through at least one tap point located between the first and second ends. The pMOS transistors and the first metal interconnect function as a decoupling capacitor.Type: ApplicationFiled: November 23, 2016Publication date: May 24, 2018Inventors: Andi ZHAO, Ramaprasath VILANGUDIPITCHAI, Dorav KUMAR
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Patent number: 9948303Abstract: In one embodiment, a voltage level shifter includes a first p-type metal-oxide-semiconductor (PMOS) transistor having a gate configured to receive an input signal in a first power domain, and a second PMOS transistor, wherein the first and second PMOS transistors are coupled in series between a supply voltage of a second power domain and a node. The voltage level shifter also includes an inverter having an input coupled to the node and an output coupled to a gate of the second PMOS transistor, and a first n-type metal-oxide-semiconductor (NMOS) transistor having a gate configured to receive the input signal in the first power domain, wherein the first NMOS transistor is coupled between the node and a ground.Type: GrantFiled: December 2, 2016Date of Patent: April 17, 2018Assignee: QUALCOMM IncorporatedInventors: Venkat Narayanan, Rakesh Vattikonda, De Lu, Ramaprasath Vilangudipitchai, Samrat Sinharoy, Rui Chen
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Publication number: 20180006651Abstract: In one embodiment, a voltage level shifter includes a first p-type metal-oxide-semiconductor (PMOS) transistor having a gate configured to receive an input signal in a first power domain, and a second PMOS transistor, wherein the first and second PMOS transistors are coupled in series between a supply voltage of a second power domain and a node. The voltage level shifter also includes an inverter having an input coupled to the node and an output coupled to a gate of the second PMOS transistor, and a first n-type metal-oxide-semiconductor (NMOS) transistor having a gate configured to receive the input signal in the first power domain, wherein the first NMOS transistor is coupled between the node and a ground.Type: ApplicationFiled: December 2, 2016Publication date: January 4, 2018Inventors: Venkat Narayanan, Rakesh Vattikonda, De Lu, Ramaprasath Vilangudipitchai, Samrat Sinharoy, Rui Chen
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Publication number: 20180006650Abstract: In one embodiment, a voltage level shifter includes a first NOR gate having a first input configured to receive a first input signal in a first power domain, a second input configured to receive an enable signal in a second power domain, a third input, and an output. The voltage level shifter also includes a second NOR gate having a first input configured to receive a second input signal in the first power domain, a second input configured to receive the enable signal in the second power domain, a third input coupled to the output of the first NOR gate, and an output coupled to the third input of the first NOR gate. The first and second NOR gates are powered by a supply voltage of the second power domain.Type: ApplicationFiled: December 2, 2016Publication date: January 4, 2018Inventors: Venkat Narayanan, Rakesh Vattikonda, De Lu, Ramaprasath Vilangudipitchai, Samrat Sinharoy, Rui Chen
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Patent number: 9859893Abstract: In one embodiment, a voltage level shifter includes a first NOR gate having a first input configured to receive a first input signal in a first power domain, a second input configured to receive an enable signal in a second power domain, a third input, and an output. The voltage level shifter also includes a second NOR gate having a first input configured to receive a second input signal in the first power domain, a second input configured to receive the enable signal in the second power domain, a third input coupled to the output of the first NOR gate, and an output coupled to the third input of the first NOR gate. The first and second NOR gates are powered by a supply voltage of the second power domain.Type: GrantFiled: December 2, 2016Date of Patent: January 2, 2018Assignee: QUALCOMM IncorporatedInventors: Venkat Narayanan, Rakesh Vattikonda, De Lu, Ramaprasath Vilangudipitchai, Samrat Sinharoy, Rui Chen