Abstract: An integrated circuit (IC) is disclosed herein for adjustable power rail multiplexing. In an example aspect, an IC includes a first power rail, a second power rail, and a load power rail. The IC further includes multiple power-multiplexer (power-mux) tiles and adjustment circuitry. The multiple power-mux tiles are coupled in series in a chained arrangement and implemented to jointly perform a power-multiplexing operation. Each power-mux tile is implemented to switch between coupling the load power rail to the first power rail and coupling the load power rail to the second power rail. The adjustment circuitry is implemented to adjust at least one order in which the multiple power-mux tiles perform at least a portion of the power-multiplexing operation.

Abstract: In an aspect of the disclosure, a MOS device for reducing routing congestion caused by using split n-well cells in a merged n-well circuit block is provided. The MOS device may include a first set of cells adjacent to each other in a first direction. The MOS device may include a second set of cells adjacent to each other in the first direction and adjacent to the first set of cells in a second direction. The second set of cells each may include a first n-well, a second n-well, and a third n-well separated from each other. The MOS device may include an interconnect extending in the first direction in the second set of cells. The interconnect may provide a voltage source to the first n-well of each of the second set of cells.

Abstract: An integrated circuit (IC) is disclosed herein for adjustable power rail multiplexing. In an example aspect, an IC includes a first power rail, a second power rail, and a load power rail. The IC further includes multiple power-multiplexer (power-mux) tiles and adjustment circuitry. The multiple power-mux tiles are coupled in series in a chained arrangement and implemented to jointly perform a power-multiplexing operation. Each power-mux tile is implemented to switch between coupling the load power rail to the first power rail and coupling the load power rail to the second power rail. The adjustment circuitry is implemented to adjust at least one order in which the multiple power-mux tiles perform at least a portion of the power-multiplexing operation.

Abstract: Systems and methods for powering up circuits are described herein. In one embodiment, a method for power up comprises comparing a voltage of a first supply rail with a voltage of a second supply rail, and determining whether the voltage of the first supply rail is within a predetermined amount of the voltage of the second supply rail for at least a predetermined period of time based on the comparison. The method also comprises initiating switching of a plurality of switches coupled between the first and second supply rails upon a determination that the voltage of the first supply rail is within the predetermined amount of the voltage of the second supply rail for at least the predetermined period of time.

Abstract: Data retention circuitry, such as at least one integrated circuit (IC), is disclosed herein for power multiplexing with flip-flops having a retention feature. In an example aspect, an IC includes a first power rail and a second power rail. The IC further includes a flip-flop and power multiplexing circuitry. The flip flop includes a master portion and a slave portion. The master portion is coupled to the first power rail for a regular operational mode and for a retention operational mode. The power multiplexing circuitry is configured to couple the slave portion to the first power rail for the regular operational mode and to the second power rail for the retention operational mode.

Abstract: A circuit including a logic gate responsive to a clock signal and to a control signal. The circuit also includes a master stage of a flip-flop. The circuit further includes a slave stage of the flip-flop responsive to the master stage. The circuit further includes an inverter responsive to the logic gate and configured to output a delayed version of the clock signal. An output of the logic gate and the delayed version of the clock signal are provided to the master stage and to the slave stage of the flip-flop. The master stage is responsive to the control signal to control the slave stage.

Abstract: An integrated circuit (IC) is disclosed having a unified control scheme and a unifying architecture for different types of retention flip-flops (RFFs). In an example aspect, an IC includes a constant power rail to provide power during a power collapse period and a collapsible power rail to cease providing power during the power collapse period. The IC also includes a positive-edge-triggered (PET) RFF and a negative-edge-triggered (NET) RFF. The PET RFF includes a master portion and a slave portion, with the slave portion coupled to the constant power rail and the master portion coupled to the collapsible power rail. The NET RFF includes master and slave portions, with the master portion coupled to the constant power rail and the slave portion coupled to the collapsible power rail. In another example aspect, a control signal based on a clock and a retention signal may be routed to both RFFs.

Abstract: An integrated circuit (IC) is disclosed herein for power management through power rail multiplexing. In an example aspect, an IC includes a first power rail, a second power rail, and a load power rail. The IC also includes a first set of transistors including first transistors that are coupled to the first power rail and a second set of transistors including second transistors that are coupled to the second power rail. The IC further includes power-multiplexer circuitry that is configured to switch access to power for the load power rail from the first power rail to the second power rail by sequentially turning off the first transistors of the first set of transistors and then sequentially turning on the second transistors of the second set of transistors.

Abstract: A standard cell IC may include a plurality of pMOS transistors each including a pMOS transistor drain, a pMOS transistor source, and a pMOS transistor gate. Each pMOS transistor drain and pMOS transistor source of the plurality of pMOS transistors may be coupled to a first voltage source. The standard cell IC may also include a plurality of nMOS transistors each including an nMOS transistor drain, an nMOS transistor source, and an nMOS transistor gate. Each nMOS transistor drain and nMOS transistor source of the plurality of nMOS transistors are coupled to a second voltage source lower than the first voltage source.

Abstract: Data retention circuitry, such as at least one integrated circuit (IC), is disclosed herein for power multiplexing with flip-flops having a retention feature. In an example aspect, an IC includes a first power rail and a second power rail. The IC further includes a flip-flop and power multiplexing circuitry. The flip flop includes a master portion and a slave portion. The master portion is coupled to the first power rail for a regular operational mode and for a retention operational mode. The power multiplexing circuitry is configured to couple the slave portion to the first power rail for the regular operational mode and to the second power rail for the retention operational mode.

Abstract: An integrated circuit (IC) is disclosed herein for power management through power rail multiplexing. In an example aspect, an IC includes a first power rail, a second power rail, and a load power rail. The IC also includes a first set of transistors including first transistors that are coupled to the first power rail and a second set of transistors including second transistors that are coupled to the second power rail. The IC further includes power-multiplexer circuitry that is configured to switch access to power for the load power rail from the first power rail to the second power rail by sequentially turning off the first transistors of the first set of transistors and then sequentially turning on the second transistors of the second set of transistors.

Abstract: A MOS device includes a number of standard cells configured to reduce routing congestions while providing area savings on the MOS device. The standard cells may be single height standard cells that share an n-type well isolated from other nearby n-type wells. The input and output signal pins of the single height standard cells may be configured in a lowest possible metal layer (e.g., M1), while the secondary power pins of the single height standard cells may be configured in a higher metal layer (e.g., M2). Interconnects supplying power to secondary power pins may be configured along vertical tracks and shared among different sets of standard cells, which may reduce the number of vertical tracks used in the MOS device. The number of available horizontal routing tracks in the MOS device may remain unaffected, since the horizontal tracks already used by the primary power/ground mesh are used for power connection.

Abstract: An integrated circuit (IC) is disclosed herein for managing power with flip-flops having a retention feature. In an example aspect, an IC includes a constant power rail, a collapsible power rail, multiple flip-flops, and power management circuitry. Each flip-flop of the multiple flip-flops includes a master portion that is coupled to the collapsible power rail and a slave portion that is coupled to the constant power rail. The power management circuitry is configured to combine a clock signal and a retention signal into a combined control signal and to provide the combined control signal to each flip-flop of the multiple flip-flops.

Abstract: Systems and methods for powering up circuits are described herein. In one embodiment, a method for power up comprises comparing a voltage of a first supply rail with a voltage of a second supply rail, and determining whether the voltage of the first supply rail is within a predetermined amount of the voltage of the second supply rail for at least a predetermined period of time based on the comparison. The method also comprises initiating switching of a plurality of switches coupled between the first and second supply rails upon a determination that the voltage of the first supply rail is within the predetermined amount of the voltage of the second supply rail for at least the predetermined period of time.

Abstract: A particular method includes receiving a retention signal. In response to receiving the retention signal, the method includes retaining state information in a non-volatile stage of a retention register and reducing power to a volatile stage of the retention register. The non-volatile stage may be powered by an external voltage source. The volatile stage may be powered by an internal voltage source.

Abstract: A MOS device includes a number of standard cells configured to reduce routing congestions while providing area savings on the MOS device. The standard cells may be single height standard cells that share an n-type well isolated from other nearby n-type wells. The input and output signal pins of the single height standard cells may be configured in a lowest possible metal layer (e.g., M1), while the secondary power pins of the single height standard cells may be configured in a higher metal layer (e.g., M2). Interconnects supplying power to secondary power pins may be configured along vertical tracks and shared among different sets of standard cells, which may reduce the number of vertical tracks used in the MOS device. The number of available horizontal routing tracks in the MOS device may remain unaffected, since the horizontal tracks already used by the primary power/ground mesh are used for power connection.

Abstract: A particular method includes receiving a retention signal. In response to receiving the retention signal, the method includes retaining state information in a non-volatile stage of a retention register and reducing power to a volatile stage of the retention register. The non-volatile stage may be powered by an external voltage source. The volatile stage may be powered by an internal voltage source.

Abstract: A layout architecture for voltage level shifters is provided. The architecture includes features of voltage level shifter cells and arrangements of the voltage level shifter cells within integrated circuits. The architecture can be used, for example, in CMOS system-on-a-chip integrated circuits implemented using metal-programmable standard cells. The architecture is also scalable for interfaces having different numbers of signals. The architecture can provide reduced area and improved performance.

Abstract: A latch-based array includes a plurality of columns and rows. Each column comprises a plurality of slave latches that all latch in parallel a master-latched data output from the column's master latch during normal operation. In a fault-testing mode of operation, one of the slaves in the column latches an inverted version of the master-latched data output while the remaining slave latches in the column latch the master-latched data output. In this fashion, the slave latches are decorrelated in a single write operation.

Abstract: A particular method includes receiving a retention signal. In response to receiving the retention signal, the method includes retaining state information in a non-volatile stage of a retention register and reducing power to a volatile stage of the retention register. The non-volatile stage may be powered by an external voltage source. The volatile stage may be powered by an internal voltage source.