Patents by Inventor Ramaswamy Ranganathan

Ramaswamy Ranganathan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9208332
    Abstract: Resource authorization policies and resource scopes may be defined separately, thereby decoupling a set of authorization rules from the scope of resources to which those rules apply. In one example, a resource includes anything that can be used in a computing environment (e.g., a file, a device, etc.). A scope describes a set of resources (e.g., all files in folder X, all files labeled “Y”, etc.). Policies describe what can be done with a resource (e.g., “read-only,” “read/write,” “delete, if requestor is a member of the admin group,” etc.). When scopes and policies have been defined, they may be linked, thereby indicating that the policy applies to any resource within the scope. When a request for the resource is made, the request is evaluated against all policies associated with scopes that contain the resource. If the conditions specified in the policies apply, then the request may be granted.
    Type: Grant
    Filed: December 24, 2010
    Date of Patent: December 8, 2015
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Paul Leach, David McPherson, Vishal Agarwal, Mark Fishel Novak, Ming Tang, Ramaswamy Ranganathan, Pranav Kukreja, Andrey Popov, Nir Ben Zvi, Arun K. Nanda
  • Patent number: 9045397
    Abstract: Described herein are high yield methods for making magnolol analogs which are 5,5?-dialkyl-bi-phenyl-2,2?-diols.
    Type: Grant
    Filed: December 20, 2011
    Date of Patent: June 2, 2015
    Assignee: Colgate-Palmolive Company
    Inventors: Ramesh Naik, Sanju Walikar, Govindarajalu Jeyaraman, Koottungalmadhom Ramaswamy Ranganathan
  • Patent number: 9000231
    Abstract: Described herein are high yield methods for making magnolol (5,5?-diallyl-biphenyl-2,2?-diol) and tetrahydro-magnolol (5,5?-dipropyl-biphenyl-2,2?-diol).
    Type: Grant
    Filed: June 20, 2011
    Date of Patent: April 7, 2015
    Assignee: Colgate-Palmolive Company
    Inventors: Ramesh Naik, Sanju Walikar, Ramesh Jayaramaiah, Vangumalla Devaki Devi, Govindarajalu Jeyaraman, Koottungalmadhom Ramaswamy Ranganathan
  • Publication number: 20140357902
    Abstract: Described herein are high yield methods for making magnolol (5,5?-diallyl-biphenyl-2,2?-diol) and tetrahydro-magnolol (5,5?-dipropyl-biphenyl-2,2?-diol).
    Type: Application
    Filed: June 20, 2011
    Publication date: December 4, 2014
    Applicant: COLGATE-PALMOLIVE COMPANY
    Inventors: Ramesh Naik, Sanju Walikar, Ramesh Jayaramaiah, Vangumalla Devaki Devi, Govindarajalu Jeyaraman, Koottungalmadhom Ramaswamy Ranganathan
  • Publication number: 20140343328
    Abstract: Described herein are high yield methods for making magnolol analogs which are 5,5?-dialkyl-bi-phenyl-2,2?-diols.
    Type: Application
    Filed: December 20, 2011
    Publication date: November 20, 2014
    Applicant: Colgate-Palmolive Company
    Inventors: Ramesh Naik, Sanju Walikar, Govindarajalu Jeyaraman, Koottungalmadhom Ramaswamy Ranganathan
  • Patent number: 8813170
    Abstract: A policy that governs access to a resource may be tested against real-world access requests before being used to control access to the resource. In one example, access to a resource is governed by a policy, referred to as an effective policy. When the policy is to be modified or replaced, the modification or replacement may become a test policy. When a request is made to access the resource, the request may be evaluated under both the effective policy and the test policy. Whether access is granted is determined under the effective policy, but the decision that would be made under the test policy is noted, and may be logged. If the test policy is determined to behave acceptably when confronted with real-world access requests, then the current effective policy may be replaced with the test policy.
    Type: Grant
    Filed: November 10, 2011
    Date of Patent: August 19, 2014
    Assignee: Microsoft Corporation
    Inventors: Mark F. Novak, Paul Leach, Vishal Agarwal, David McPherson, Sunil Gottumukkala, Jignesh Shah, Arun K. Nanda, Nir Ben Zvi, Pranav Kukreja, Ramaswamy Ranganathan
  • Publication number: 20130125199
    Abstract: A policy that governs access to a resource may be tested against real-world access requests before being used to control access to the resource. In one example, access to a resource is governed by a policy, referred to as an effective policy. When the policy is to be modified or replaced, the modification or replacement may become a test policy. When a request is made to access the resource, the request may be evaluated under both the effective policy and the test policy. Whether access is granted is determined under the effective policy, but the decision that would be made under the test policy is noted, and may be logged. If the test policy is determined to behave acceptably when confronted with real-world access requests, then the current effective policy may be replaced with the test policy.
    Type: Application
    Filed: November 10, 2011
    Publication date: May 16, 2013
    Applicant: MICROSOFT CORPORATION
    Inventors: Mark F. Novak, Paul Leach, Vishal Agarwal, David McPherson, Sunil Gottumukkala, Jignesh Shah, Arun K. Nanda, Nir Ben Zvi, Pranav Kukreja, Ramaswamy Ranganathan
  • Patent number: 8283499
    Abstract: The present invention relates the use of 2,3-dihalonaphthoquinone compounds of Formula I wherein R1 and R2 are leaving groups like halogens selected from the group comprising Cl, Br, I and F and the R1 and R2 may be the same halogen or may contain different halogen groups, or sulphonyl groups, for making napthoquinone compounds of Formula IA wherein X is any aryl, heteroaryl, alkyl, cyclohexyl, substituted cylohexyl groups and the like.
    Type: Grant
    Filed: March 6, 2009
    Date of Patent: October 9, 2012
    Assignee: Alkem Laboratories Limited
    Inventors: Sanjay Sukumar Saralya, Shashikumar Hiriyalu Somashekar, Shashiprabha, Shridhara Kanakamajalu, Koottungalmadhom Ramaswamy Ranganathan, Veerasamy Ananthalakshmi, Govindarajalu Jeyaraman, Kothapalli Sundarraja Rao, Kuppuswamy Nagarajan
  • Publication number: 20120167158
    Abstract: Resource authorization policies and resource scopes may be defined separately, thereby decoupling a set of authorization rules from the scope of resources to which those rules apply. In one example, a resource includes anything that can be used in a computing environment (e.g., a file, a device, etc.). A scope describes a set of resources (e.g., all files in folder X, all files labeled “Y”, etc.). Policies describe what can be done with a resource (e.g., “read-only,” “read/write,” “delete, if requestor is a member of the admin group,” etc.). When scopes and policies have been defined, they may be linked, thereby indicating that the policy applies to any resource within the scope. When a request for the resource is made, the request is evaluated against all policies associated with scopes that contain the resource. If the conditions specified in the policies apply, then the request may be granted.
    Type: Application
    Filed: December 24, 2010
    Publication date: June 28, 2012
    Applicant: MICROSOFT CORPORATION
    Inventors: Paul Leach, David McPherson, Vishal Agarwal, Mark Fishel Novak, Ming Tang, Ramaswamy Ranganathan, Pranav Kukreja, Andrey Popov, Nir Ben Zvi, Arun K. Nanda
  • Patent number: 8163643
    Abstract: A semiconductor device is disclosed that has a die and a substrate having a die attachment area with a perimeter. A layer of solder connects the substrate and the die, the solder layer having at least one vent channel connected to the perimeter of the die attachment area, wherein the maximum distance from any point in the solder layer to the nearest free surface of the solder at a vent channel or at the perimeter of the die is less than the distance from the center of the die to the nearest edge of the die.
    Type: Grant
    Filed: May 4, 2010
    Date of Patent: April 24, 2012
    Assignee: Linear Technology Corporation
    Inventors: Maurice O. Othieno, Ramaswamy Ranganathan, Frederick E. Beville, David A. Pruitt, William D. Griffitts
  • Publication number: 20110004024
    Abstract: The present invention relates the use of 2,3-dihalonaphthoquinone compounds of Formula I wherein R1 and R2 are leaving groups like halogens selected from the group comprising Cl, Br, I and F and the R1 and R2 may be the same halogen or may contain different halogen groups, or sulphonyl groups, for making napthoquinone compounds of Formula IA wherein X is any aryl, heteroaryl, alkyl, cyclohexyl, substituted cylohexyl groups and the like.
    Type: Application
    Filed: March 6, 2009
    Publication date: January 6, 2011
    Applicant: ALKEM LABORATORIES LIMITED
    Inventors: Sanjay Sukumar Saralya, Shashikumar Hiriyalu Somashekar, Shashiprabha, Shridhara Kanakamajalu, Koottungalmadhom Ramaswamy Ranganathan, Veerasamy Ananthalakshmi, Govindarajalu Jeyaraman, Kothapalli Sundarraja Rao, Kuppuswamy Nagarajan
  • Patent number: 7531442
    Abstract: Different ways to reduce or eliminate the IMC cracking issues in wire bonded parts, including: changing to more compressive dielectric films for top, R1, and R2; changing the top passivation film stacks to more compressive films; changing the low k film to a higher compressive film; reducing the R layer thickness and pattern density to reduce tensile stress; and minimizing anneal and dielectric deposition temperatures. Each of the methods can be used individually or in combination with each other to reduce overall tensile stresses in the Cu/low-k wafer thus reducing or eliminating the IMC cracking issue currently seen in the post wire bonded parts.
    Type: Grant
    Filed: November 30, 2005
    Date of Patent: May 12, 2009
    Assignee: LSI Corporation
    Inventors: Jayanthi Pallinti, Dilip Vijay, Hemanshu Bhatt, Sey-Shing Sun, Hong Ying, Chiyi Kao, Peter Burke, Ramaswamy Ranganathan, Qwai Low
  • Publication number: 20070123024
    Abstract: Different ways to reduce or eliminate the IMC cracking issues in wire bonded parts, including: changing to more compressive dielectric films for top, R1, and R2; changing the top passivation film stacks to more compressive films; changing the low k film to a higher compressive film; reducing the R layer thickness and pattern density to reduce tensile stress; and minimizing anneal and dielectric deposition temperatures. Each of the methods can be used individually or in combination with each other to reduce overall tensile stresses in the Cu/low-k wafer thus reducing or eliminating the IMC cracking issue currently seen in the post wire bonded parts.
    Type: Application
    Filed: November 30, 2005
    Publication date: May 31, 2007
    Inventors: Jayanthi Pallinti, Dilip Vijay, Hemanshu Bhatt, Sey-Shing Sun, Hong Ying, Chiyi Kao, Peter Burke, Ramaswamy Ranganathan, Qwai Low
  • Patent number: 6998638
    Abstract: An integrated circuit having a crack detection structure. A control structure is formed having interleaved electrically conductive layers and non electrically conductive layers in a vertical orientation. Electrically conductive vias are disposed vertically through all of the non electrically conductive layers, which vias electrically connect all of the electrically conductive layers one to another. A test structure is formed having a bonding pad for probing and bonding, with underlying interleaved electrically conductive layers and non electrically conductive layers disposed in a vertical orientation. At least one of the non electrically conductive layers has no vias formed therein, simulating active circuitry under other bonding pads of the integrated circuit. At least one of the interleaved electrically conductive layers of the control structure extends from within the control structure to within the test structure as a sensing layer.
    Type: Grant
    Filed: May 28, 2004
    Date of Patent: February 14, 2006
    Assignee: LSI Logic Corporation
    Inventors: Qwai H. Low, Ramaswamy Ranganathan, Anwar Ali, Tauman T. Lau
  • Patent number: 6991147
    Abstract: A method for insulating a bonding wire that includes the steps of attaching a bonding wire to a bond pad and coating the bonding wire with an insulating liquid while drawing the bonding wire through a bond tool from the bond pad to a package lead.
    Type: Grant
    Filed: August 18, 2003
    Date of Patent: January 31, 2006
    Assignee: LSI Logic Corporation
    Inventors: Chok J. Chia, Owai H. Low, Ramaswamy Ranganathan
  • Patent number: 6963138
    Abstract: An integrated circuit with a pressure resistant current carrying structure having electrically conductive layers for carrying current. A first electrically nonconductive material at least partially surrounds the electrically conductive layers, and provides electrical insulation between the electrically conductive layers. The first electrically nonconductive material has a first degree of fragility and a first dielectric constant. A second electrically nonconductive material is disposed in a pattern within the first electrically nonconductive material and between the electrically conductive layers, and provides structural support for the first electrically nonconductive material between the electrically conductive layers. The second electrically nonconductive material has a second degree of fragility that is less than the first degree of fragility and a second dielectric constant that is greater than the first dielectric constant.
    Type: Grant
    Filed: February 3, 2003
    Date of Patent: November 8, 2005
    Assignee: LSI Logic Corporation
    Inventors: Qwai H. Low, Chok J. Chia, Ramaswamy Ranganathan, Tauman T. Lau
  • Patent number: 6861748
    Abstract: A test structure for an integrated circuit having a first underlying conductive layer. A first nonconductive layer is disposed over the first underlying conductive layer, and a first overlying conductive layer is disposed over the first nonconductive layer. First conductive vias form electrical connections between the first underlying conductive layer and the first overlying conductive layer. A second overlying conductive layer is disposed over the first nonconductive layer, but the second overlying conductive layer does not make electrical connections to the first underlying conductive layer. The test structure also has a second underlying conductive layer. A second nonconductive layer is disposed over the second underlying conductive layer, with a third overlying conductive layer disposed over the second nonconductive layer. The third overlying conductive layer does not make electrical connections to the second underlying conductive layer.
    Type: Grant
    Filed: November 18, 2002
    Date of Patent: March 1, 2005
    Assignee: LSI Logic Corporation
    Inventors: Qwai H. Low, Ramaswamy Ranganathan, Rey Torcuato
  • Patent number: 6861343
    Abstract: An integrated circuit having a top passivation layer and bonding pads, where the improvement is a metal layer overlying all of the integrated circuit. The metal layer overlies the top passivation layer and is not in electrical contact with any of the bonding pads. In this manner, there is a structure that is added to the integrated circuit which has a relatively high thermal conductivity, and which also has a relatively high structural strength. With these two added properties, the occurrence of stress cracks, such as those induced by plastic molded packages, is reduced, and hot spots tend to be dissipated. Thus, the overlying metal layer tends to improve the reliability of the integrated circuit.
    Type: Grant
    Filed: October 9, 2002
    Date of Patent: March 1, 2005
    Inventors: Chok J. Chia, Qwai H. Low, Ramaswamy Ranganathan
  • Patent number: 6825563
    Abstract: A bonding pad structure having an electrically conductive capping layer. An electrically conductive first supporting layer having major orthogonal sides is disposed under the electrically conductive capping layer. The electrically conductive first supporting layer is configured as a sheet having slotted voids in a first direction. An electrically conductive second supporting layer having major orthogonal sides is disposed under the electrically conductive first supporting layer. The electrically conductive second supporting layer is configured as a sheet having slotted voids in a second direction. The first direction and the second direction are associated one with another by being disposed at a positive value and a negative value of an angle, where the angle is neither zero nor ninety degrees with respect to the major orthogonal sides of the electrically conductive first supporting layer and the electrically conductive second supporting layer.
    Type: Grant
    Filed: October 9, 2003
    Date of Patent: November 30, 2004
    Assignee: LSI Logic Corporation
    Inventors: Ramaswamy Ranganathan, Maurice Othieno, Qwai H. Low
  • Publication number: 20040217487
    Abstract: An integrated circuit having a crack detection structure. A control structure is formed having interleaved electrically conductive layers and non electrically conductive layers in a vertical orientation. Electrically conductive vias are disposed vertically through all of the non electrically conductive layers, which vias electrically connect all of the electrically conductive layers one to another. A test structure is formed having a bonding pad for probing and bonding, with underlying interleaved electrically conductive layers and non electrically conductive layers disposed in a vertical orientation. At least one of the non electrically conductive layers has no vias formed therein, simulating active circuitry under other bonding pads of the integrated circuit. At least one of the interleaved electrically conductive layers of the control structure extends from within the control structure to within the test structure as a sensing layer.
    Type: Application
    Filed: May 28, 2004
    Publication date: November 4, 2004
    Inventors: Qwai H. Low, Ramaswamy Ranganathan, Anwar Ali, Tauman T. Lau