Abstract: A bonding pad structure having an electrically conductive capping layer. An electrically conductive first supporting layer is disposed immediately under the electrically conductive capping layer, without any intervening layers between the electrically conductive capping layer and the electrically conductive first supporting layer. The electrically conductive first supporting layer is configured as one of a sheet having no voids and a sheet having slotted voids in a first direction. An electrically conductive second supporting layer is disposed under the electrically conductive first supporting layer. The electrically conductive second supporting layer is configured as one of a sheet having slotted voids in the first direction, a sheet having slotted voids in a second direction, and a sheet having checkerboard voids.

Abstract: A method for insulating a bonding wire that includes the steps of attaching a bonding wire to a bond pad and coating the bonding wire with an insulating liquid while drawing the bonding wire through a bond tool from the bond pad to a package lead.

Abstract: A wire bond assembly includes a multitude of bond pads arranged in an array on the surface of a die among the active circuitry and wires for electrically connecting the bond pads on the die to the substrate. As the bond pads on the die are not limited to the perimeter of the die a greater density of bond pads can be achieved and therefore the overall dimensions of the die can be reduced.

Abstract: An integrated circuit having a crack detection structure. A control structure is formed having interleaved electrically conductive layers and non electrically conductive layers in a vertical orientation. Electrically conductive vias are disposed vertically through all of the non electrically conductive layers, which vias electrically connect all of the electrically conductive layers one to another. A test structure is formed having a bonding pad for probing and bonding, with underlying interleaved electrically conductive layers and non electrically conductive layers disposed in a vertical orientation. At least one of the non electrically conductive layers has no vias formed therein, simulating active circuitry under other bonding pads of the integrated circuit. At least one of the interleaved electrically conductive layers of the control structure extends from within the control structure to within the test structure as a sensing layer.

Abstract: An integrated circuit with a pressure resistant current carrying structure having electrically conductive layers for carrying current. A first electrically nonconductive material at least partially surrounds the electrically conductive layers, and provides electrical insulation between the electrically conductive layers. The first electrically nonconductive material has a first degree of fragility and a first dielectric constant. A second electrically nonconductive material is disposed in a pattern within the first electrically nonconductive material and between the electrically conductive layers, and provides structural support for the first electrically nonconductive material between the electrically conductive layers. The second electrically nonconductive material has a second degree of fragility that is less than the first degree of fragility and a second dielectric constant that is greater than the first dielectric constant.

Abstract: An integrated circuit, including a substrate with circuitry formed therein, where the substrate has a peripheral edge. Also included are a top most electrically conductive layer and an underlying electrically conductive layer. Outer bonding pads are disposed in an outer ring, and are formed within the top most layer. Inner bonding pads are disposed in an inner ring, and are formed within the top most layer. Inner connectors electrically connect the inner bonding pads to the circuitry. The inner connectors are formed within the underlying layer, and have a width that is less than the width of the inner bonding pads, thereby defining a gap between the inner connectors. Outer connectors electrically connect the outer bonding pads to the circuitry. The outer connectors are formed within the underlying layer, and have a width that is less than the width of the gap between the inner connectors.

Abstract: A test structure for an integrated circuit having a first underlying conductive layer. A first nonconductive layer is disposed over the first underlying conductive layer, and a first overlying conductive layer is disposed over the first nonconductive layer. First conductive vias form electrical connections between the first underlying conductive layer and the first overlying conductive layer. A second overlying conductive layer is disposed over the first nonconductive layer, but the second overlying conductive layer does not make electrical connections to the first underlying conductive layer. The test structure also has a second underlying conductive layer. A second nonconductive layer is disposed over the second underlying conductive layer, with a third overlying conductive layer disposed over the second nonconductive layer. The third overlying conductive layer does not make electrical connections to the second underlying conductive layer.

Abstract: A die wire bonded to a semiconductor substrate includes insulated signal wire, insulated power wires and uninsulated ground wires between the die and the semiconductor substrate. A conductive material is provided over the signal, power and ground wire bonds which provides an electrical connection between the uninsulated ground wires. The conductive material follows the same profile as the wire bonds and provides a controlled impedance environment for the signal wirebonds.

Abstract: An integrated circuit having a top passivation layer and bonding pads, where the improvement is a metal layer overlying all of the integrated circuit. The metal layer overlies the top passivation layer and is not in electrical contact with any of the bonding pads. In this manner, there is a structure that is added to the integrated circuit which has a relatively high thermal conductivity, and which also has a relatively high structural strength. With these two added properties, the occurrence of stress cracks, such as those induced by plastic molded packages, is reduced, and hot spots tend to be dissipated. Thus, the overlying metal layer tends to improve the reliability of the integrated circuit.

Abstract: An integrated circuit having a crack detection structure. A control structure is formed having interleaved electrically conductive layers and non electrically conductive layers in a vertical orientation. Electrically conductive vias are disposed vertically through all of the non electrically conductive layers, which vias electrically connect all of the electrically conductive layers one to another. A test structure is formed having a bonding pad for probing and bonding, with underlying interleaved electrically conductive layers and non electrically conductive layers disposed in a vertical orientation. At least one of the non electrically conductive layers has no vias formed therein, simulating active circuitry under other bonding pads of the integrated circuit. At least one of the interleaved electrically conductive layers of the control structure extends from within the control structure to within the test structure as a sensing layer.

Abstract: A method for insulating a bonding wire that includes the steps of attaching a bonding wire to a bond pad and coating the bonding wire with an insulating liquid while drawing the bonding wire through a bond tool from the bond pad to a package lead.

Abstract: An integrated circuit topography is provided which includes at least two rows of bonding pads. Each row of bonding pads is attributed a row of probe pads. One row of probe pads is contained within the scribe area and suffices as a sacrificial row of probe pads. The other row of probe pads is placed toward the interior of the integrated circuit. The rows of bonding pads and probe pads extend along parallel axis around all four sides of the integrated circuit. Every other bonding pad within one row of bonding pads is connected to every other probe pad within the scribe area, and every other bonding pad within the other rows of bonding pads is connected to every probe pad within the row of probe pads interior to the integrated circuit. This allows a fan-out configuration of the bonding pads to probe pads for purposes of probing electrical performance of the integrated circuit without having to use selected ones of the bonding pads.

Abstract: An improved tape substrate design for a semiconductor package is disclosed. The tape substrate semiconductor package includes a plurality of die pads, a plurality of vias, and a pattern of metal traces interconnected between the die pads and the vias to form circuitry on the tape substrate. According to the method and apparatus of the present invention an extra metal layer is added at the circuitry to increase rigidity of the tape substrate, thereby reducing warpage without adding to the thickness of the tape substrate package.

Abstract: According to the present invention, a method for creating a package for a semiconductor die, the package comprising a flexible tape, comprises the following steps. A support with an opening has a plurality of arms extending through at a portion of the opening. For example, for a square opening, there may be eight arms, two extending from each side of the opening. The arms preferably form a “z” shape or some other shape with a transverse component. The flexible tape is then attached to the ends of the arms within the opening such that the flexible tape is supported by the arms. A die is attached to the flexible tape, the die is preferably covered with a molding compound, and the die/flexible tape assembly is scribed from the support, thereby creating an individual package.

Abstract: A method of forming a low loop height wire interconnection in a semiconductor package including a die having a multiple row bond pad layout, and a wire bonded electrical interconnection formed using the method consists of the steps: forming a first ball bond from a first wire at a first bonding location; looping the first wire to a first bond pad of a die; forming a first stitch bond between the first wire and the first bond pad; forming a second ball bond from a second wire at a second bond pad of the die; looping the second wire to a second bonding location, wherein the second wire does not contact the first wire; and forming a second stitch bond between the second wire and the second bonding location.

Abstract: A semiconductor package is present along with an associated method. The package comprises a substrate with a top surface and a bottom surface, the substrate having a plurality of electrically conductive vias extending from the top surface of the substrate to the bottom surface of the substrate. A semiconductor device having an active surface, the active surface having a plurality of bonding pads, is attached to the substrate by an adhesive that bas holes that align with the vias. The vias are also aligned with the bonding pads. Solder serves to electrically and mechanically couple each of the bonding pads with a corresponding via. Each of the vias, in turn, is coupled to a solder ball formed on the bottom of the substrate.

Abstract: The subject method comprises providing a semiconductor package and a semiconductor package substrate having respective first and second major sides. A stiffener member, which is attachable to the semiconductor package substrate, is employed for purposes of minimizing package warpage. The stiffener member is attached to the semiconductor package substrate to provide the requisite support for the semiconductor package substrate during the assembly process and thereby counteract the sources of the package warpage problem. A protective outer layer can be optionally added to the subject system.

Abstract: Cooperative patterns are formed in stencils and/or substrates that facilitate the monitoring and control of the circuit assembly process. A pattern of successively-larger etch blocks receives a corresponding pattern of same-size solder blocks; solder reflow problems are indicated when either too many or too few etch blocks are completely covered by solder after reflow. A pattern of same-size etch blocks receives a corresponding pattern of successively-larger solder blocks; problems with solder stencil clogging are indicated when smaller ones of the etch blocks do not receive solder paste during stenciling. Finally, component beacon openings or translucent areas are made in the electronics assembly at component locations. After component placement, the board is appropriately lit, and any uncovered openings indicate missing or grossly misaligned components.

Abstract: Etch features are included on a printed circuit (PC) board to be used in monitoring and controlling assembly processes such as soldering. A vernier pattern of etch blocks receives corresponding solder blocks during solder paste screening; misalignment of the solder stencil to the PC board is indicated by an easily-seen interference pattern of spaces created by the superimposed etch and solder blocks. The degree of misalignment can be determined by measuring the distance between the center of the interference pattern and a reference etch block. Also, a scale pattern of etch receives a bar of solder paste; misalignment in the direction orthogonal to the long axis of the scale is indicated by the location of the intersection of the long axis and the solder bar.