Patents by Inventor Ramesh Kakkad
Ramesh Kakkad has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20180166603Abstract: Thin film silicon photovoltaic cell arrangements that include a heavily doped p-type polycrystalline silicon layer spaced-apart from the substrate and bottom electrode in order to reduce grain defects by initiating crystallization at a location far from the substrate. This is accomplished by forming a device structure incorporating such amorphous silicon films on a substrate and annealing at elevated temperature to crystallize the a-Si films such that the crystallization of the a-Si starts within the spaced-apart heavily doped p-type layer and proceeds through the intrinsic silicon layer.Type: ApplicationFiled: December 6, 2017Publication date: June 14, 2018Inventor: Ramesh Kakkad
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Patent number: 8294840Abstract: A system for displaying images, having a display panel, comprising: a lower substrate with a first surface, wherein the first surface is divided into a pixel area and a driver area; a peripheral circuit within the driver area on the first surface; at least one thin film transistor is formed in the pixel area, wherein the thin film transistor comprises an active layer, a gate dielectric layer overlying the active layer, and a gate electrode overlying the gate dielectric layer, and the active layer has source and drain regions; a first transparent electrode layer directly overlapped on a portion of the drain region, electrically connected thereto; and a second transparent electrode pattern is disposed on the gate dielectric layer, opposing the first transparent electrode layer.Type: GrantFiled: March 19, 2008Date of Patent: October 23, 2012Assignee: Chimei Innolux CorporationInventors: Ramesh Kakkad, Chieh-Wen Lin
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Patent number: 8045082Abstract: A system for display images comprising a thin film transistor array substrate is disclosed. The system for display images comprises a substrate having a pixel area, a source/drain region overlying the substrate within an active layer in the pixel area, a bottom electrode overlying the substrate in the pixel area, a top electrode overlying the bottom electrode, a first dielectric layer disposed on the active layer, a second dielectric layer disposed on the first dielectric layer, wherein the second dielectric layer is disposed between the bottom electrode and the top electrode and a gate disposed overlying the active layer, wherein the first and second dielectric layers are interposed between the gate and the active layer.Type: GrantFiled: March 20, 2008Date of Patent: October 25, 2011Assignee: Chimei Innolux CorporationInventors: Ramesh Kakkad, Hsiao-Wei Kao, Chung-Sheng Lin, Chih-Chung Liu
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Patent number: 7964456Abstract: A method of fabricating a polysilicon thin film produces a polysilicon thin film which is used to make a thin film transistor. The method includes depositing a silicon film containing amorphous silicon on a substrate, and performing thermal treatment on the silicon film at a predetermined temperature in an H2O atmosphere. Accordingly, the crystallization temperature and thermal treatment time are decreased when the amorphous silicon is crystallized by a solid phase crystallization method, and this prevents the substrate from being bent due to application of a thermal treatment process for a long time and at a high temperature. As a result of the invention, a polysilicon thin film having superior crystallization properties is obtained. Use of the polysilicon thin film in a thin film transistor results in the reduction of defects in the thin film resistor.Type: GrantFiled: January 12, 2005Date of Patent: June 21, 2011Assignee: Samsung Mobile Display Co., Ltd.Inventor: Ramesh Kakkad
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Patent number: 7943447Abstract: The present invention includes methods to crystallize amorphous silicon. A structure including a conductive film with at least one conductive layer in thermal contact with an amorphous silicon (a-Si) layer to be crystallized is exposed to an alternating or varying magnetic field. The conductive film is more easily heated by the alternative or varying magnetic field, which, in-turn, heats the a-Si film and crystallizes it while keeping the substrate at a low enough temperature to avoid damage to or bending of the substrate. The method can be applied to the fabrication of many semiconductor devices, including thin film transistors and solar cells.Type: GrantFiled: August 1, 2008Date of Patent: May 17, 2011Inventor: Ramesh Kakkad
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Patent number: 7696030Abstract: A method of fabricating a semiconductor device and a semiconductor device fabricated by the same method are disclosed. The method includes: depositing a silicon layer containing amorphous silicon on a substrate using any one of a plasma enhanced chemical vapor deposition (PECVD) method and a low pressure chemical vapor deposition (LPCVD) method; annealing the silicon layer in an H2O atmosphere at a certain temperature to form a polycrystalline silicon layer; forming a gate insulating layer on the polycrystalline silicon layer; forming impurity regions in the polycrystalline silicon layer to define source and drain regions; and activating the impurity regions. Thus, it is possible to provide a semiconductor device, in which the substrate is prevented from being bent and polycrystalline silicon constituting a semiconductor layer is excellent.Type: GrantFiled: March 18, 2005Date of Patent: April 13, 2010Assignee: Samsung Mobile Display Co., Ltd.Inventors: Ramesh Kakkad, Yong-Seog Kim
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Patent number: 7670886Abstract: A method of fabricating a polysilicon film includes: forming a seed layer on a surface of a substrate; forming a silicon layer over the surface of the seed layer; and performing a laser annealing process to transform the silicon layer into a polysilicon layer at a laser energy equal to or greater than that needed to cause complete melting of the silicon layer.Type: GrantFiled: June 22, 2006Date of Patent: March 2, 2010Assignee: TPO Displays Corp.Inventor: Ramesh Kakkad
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Publication number: 20090278121Abstract: A system for displaying images includes a thin film transistor array substrate including a substrate with thin film transistors array and at least one light-sensing element containing an amorphous silicon layer formed on the substrate, wherein the light-sensing element has a current flow direction perpendicular to the substrate.Type: ApplicationFiled: April 21, 2009Publication date: November 12, 2009Applicant: TPO Displays Corp.Inventors: Ramesh Kakkad, Keiichi Sano, Fu-Yuan Hsueh, Chih-Chung Liu, Sheng-Wen Chang
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Publication number: 20090237580Abstract: A system for display images comprising a thin film transistor array substrate is disclosed. The system for display images comprises a substrate having a pixel area, a source/drain region overlying the substrate within an active layer in the pixel area, a bottom electrode overlying the substrate in the pixel area, a top electrode overlying the bottom electrode, a first dielectric layer disposed on the active layer, a second dielectric layer disposed on the first dielectric layer, wherein the second dielectric layer is disposed between the bottom electrode and the top electrode and a gate disposed overlying the active layer, wherein the first and second dielectric layers are interposed between the gate and the active layer.Type: ApplicationFiled: March 20, 2008Publication date: September 24, 2009Applicant: TPO Displays Corp.Inventors: Ramesh KAKKAD, Hsiao-Wei KAO, Chung-Sheng LIN, Chih-Chung LIU
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Publication number: 20090237582Abstract: A system for displaying images, having a display panel, comprising: a lower substrate with a first surface, wherein the first surface is divided into a pixel area and a driver area; a peripheral circuit within the driver area on the first surface; at least one thin film transistor is formed in the pixel area, wherein the thin film transistor comprises an active layer, a gate dielectric layer overlying the active layer, and a gate electrode overlying the gate dielectric layer, and the active layer has source and drain regions; a first transparent electrode layer directly overlapped on a portion of the drain region, electrically connected thereto; and a second transparent electrode pattern is disposed on the gate dielectric layer, opposing the first transparent electrode layer.Type: ApplicationFiled: March 19, 2008Publication date: September 24, 2009Applicants: TPO Displays Corp.Inventors: Ramesh KAKKAD, Chieh-Wen Lin
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Patent number: 7544550Abstract: A semiconductor device and method of fabricating the same are provided. The method includes: depositing a silicon layer containing amorphous silicon on a substrate; defining source and drain regions by doping the silicon layer with impurity ions; crystallizing the amorphous silicon by an annealing process under an atmosphere of H2O at a predetermined temperature, and at the same time activating the impurity ions to form a semiconductor layer; forming a gate insulating layer over the entire surface of the substrate having the semiconductor layer; and forming a gate electrode on the gate insulating layer in correspondence with a channel region of the semiconductor layer, in which the annealing process is simplified by crystallizing the polycrystalline silicon and at the same time activating the impurity ions, thereby preventing the substrate from being deformed due to high temperature during the annealing process.Type: GrantFiled: March 18, 2005Date of Patent: June 9, 2009Assignee: Samsung Mobile Display Co., Ltd.Inventors: Ramesh Kakkad, Yong-Seog Kim
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Patent number: 7507648Abstract: A method by which solid phase crystallization (SPC) thermal budget for crystallizing an undoped (or a lightly doped) amorphous Si (a-Si) is significantly reduced. First, a composite layer structure consisting of an undoped (or a lightly doped) a-Si layer and a heavily doped (either p-type or n-type) a-Si layer is formed and it is subsequently annealed at an elevated temperature. The solid phase crystallization starts from the heavily doped amorphous silicon layer at a substantially reduced thermal budget and proceeds to crystallize the undoped amorphous silicon layer in contact with the heavily doped film at reduced thermal budget. The method can be applied to form poly silicon thin film transistor at reduced thermal budgets.Type: GrantFiled: June 20, 2006Date of Patent: March 24, 2009Inventor: Ramesh Kakkad
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Publication number: 20090042343Abstract: The present invention includes methods to crystallize amorphous silicon. A structure including a conductive film with at least one conductive layer in thermal contact with an amorphous silicon (a-Si) layer to be crystallized is exposed to an alternating or varying magnetic field. The conductive film is more easily heated by the alternative or varying magnetic field, which, in-turn, heats the a-Si film and crystallizes it while keeping the substrate at a low enough temperature to avoid damage to or bending of the substrate. The method can be applied to the fabrication of many semiconductor devices, including thin film transistors and solar cells.Type: ApplicationFiled: August 1, 2008Publication date: February 12, 2009Inventor: Ramesh Kakkad
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Patent number: 7465614Abstract: A semiconductor device and method of fabricating the same are provided. The method includes: depositing a silicon layer containing amorphous silicon on a substrate; partially crystallizing the amorphous silicon by applying an annealing process to the silicon layer under an atmosphere of H2O at a predetermined temperature; forming a polycrystalline silicon layer by applying an laser annealing process to the partially crystallized amorphous silicon layer; forming a gate insulating layer on the polycrystalline silicon layer; and forming a gate electrode on the gate insulating layer, so that a substrate is prevented from being bent due to high temperature crystallization while the amorphous silicon is crystallized through an SPC process, thereby reducing defects of the thin film transistor.Type: GrantFiled: March 18, 2005Date of Patent: December 16, 2008Assignee: Samsung SDI Co., Ltd.Inventor: Ramesh Kakkad
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Publication number: 20070298595Abstract: A method of fabricating a polysilicon film includes: forming a seed layer on a surface of a substrate; forming a silicon layer over the surface of the seed layer; and performing a laser annealing process to transform the silicon layer into a polysilicon layer at a laser energy equal to or greater than that needed to cause complete melting of the silicon layer.Type: ApplicationFiled: June 22, 2006Publication date: December 27, 2007Inventor: Ramesh Kakkad
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Publication number: 20070004185Abstract: A method by which solid phase crystallization (SPC) thermal budget for crystallizing an undoped (or a lightly doped) amorphous Si (a-Si) is significantly reduced. First, a composite layer structure consisting of an undoped (or a lightly doped) a-Si layer and a heavily doped (either p-type or n-type) a-Si layer is formed and it is subsequently annealed at an elevated temperature. The solid phase crystallization starts from the heavily doped amorphous silicon layer at a substantially reduced thermal budget and proceeds to crystallize the undoped amorphous silicon layer in contact with the heavily doped film at reduced thermal budget. The method can be applied to form poly silicon thin film transistor at reduced thermal budgets.Type: ApplicationFiled: June 20, 2006Publication date: January 4, 2007Inventor: Ramesh Kakkad
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Publication number: 20060017052Abstract: A semiconductor device and method of fabricating the same are provided. The method includes: depositing a silicon layer containing amorphous silicon on a substrate; partially crystallizing the amorphous silicon by applying an annealing process to the silicon layer under an atmosphere of H2O at a predetermined temperature; forming a polycrystalline silicon layer by applying an laser annealing process to the partially crystallized amorphous silicon layer; forming a gate insulating layer on the polycrystalline silicon layer; and forming a gate electrode on the gate insulating layer, so that a substrate is prevented from being bent due to high temperature crystallization while the amorphous silicon is crystallized through an SPC process, thereby reducing defects of the thin film transistor.Type: ApplicationFiled: March 18, 2005Publication date: January 26, 2006Inventor: Ramesh Kakkad
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Publication number: 20060003502Abstract: A semiconductor device and method of fabricating the same are provided. The method includes: depositing a silicon layer containing amorphous silicon on a substrate; defining source and drain regions by doping the silicon layer with impurity ions; crystallizing the amorphous silicon by an annealing process under an atmosphere of H2O at a predetermined temperature, and at the same time activating the impurity ions to form a semiconductor layer; forming a gate insulating layer over the entire surface of the substrate having the semiconductor layer; and forming a gate electrode on the gate insulating layer in correspondence with a channel region of the semiconductor layer, in which the annealing process is simplified by crystallizing the polycrystalline silicon and at the same time activating the impurity ions, thereby preventing the substrate from being deformed due to high temperature during the annealing process.Type: ApplicationFiled: March 18, 2005Publication date: January 5, 2006Inventors: Ramesh Kakkad, Yong-Seog Kim
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Publication number: 20060003501Abstract: A method of fabricating a semiconductor device and a semiconductor device fabricated by the same method are disclosed. The method includes: depositing a silicon layer containing amorphous silicon on a substrate using any one of a plasma enhanced chemical vapor deposition (PECVD) method and a low pressure chemical vapor deposition (LPCVD) method; annealing the silicon layer in an H2O atmosphere at a certain temperature to form a polycrystalline silicon layer; forming a gate insulating layer on the polycrystalline silicon layer; forming impurity regions in the polycrystalline silicon layer to define source and drain regions; and activating the impurity regions. Thus, it is possible to provide a semiconductor device, in which the substrate is prevented from being bent and polycrystalline silicon constituting a semiconductor layer is excellent.Type: ApplicationFiled: March 18, 2005Publication date: January 5, 2006Inventors: Ramesh Kakkad, Yong-Seog Kim
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Publication number: 20050186720Abstract: A method of fabricating a polysilicon thin film produces a polysilicon thin film which is used to make a thin film transistor. The method includes depositing a silicon film containing amorphous silicon on a substrate, and performing thermal treatment on the silicon film at a predetermined temperature in an H2O atmosphere. Accordingly, the crystallization temperature and thermal treatment time are decreased when the amorphous silicon is crystallized by a solid phase crystallization method, and this prevents the substrate from being bent due to application of a thermal treatment process for a long time and at a high temperature. As a result of the invention, a polysilicon thin film having superior crystallization properties is obtained. Use of the polysilicon thin film in a thin film transistor results in the reduction of defects in the thin film resistor.Type: ApplicationFiled: January 12, 2005Publication date: August 25, 2005Inventor: Ramesh Kakkad