Patents by Inventor Ramesh Raghavan
Ramesh Raghavan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10184644Abstract: A bracket for use with a recessed light fixture includes a side wall. A first bendable tab is positioned in the side wall. A second bendable tab is positioned in the side wall, the second tab being offset from the first tab. A retainer extends from the side wall.Type: GrantFiled: April 18, 2016Date of Patent: January 22, 2019Assignee: Hubbell IncorporatedInventors: Nancy R. Stathes, Federico Collado, Ramesh Raghavan, Shailesh Naik, Michael Swern
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Patent number: 10168012Abstract: A modular vapor-tight light fixture is provided herein which generally includes first and second vapor-tight light modules, and a coupling for connecting the first and second vapor-tight light modules. Each of the vapor-tight light modules includes: a channel housing; a lens secured to the channel housing; a plurality of solid state light generating elements; and, first and second end caps. Each of the channel housings includes first and second rails which each define a mounting channel. The coupling includes mounting strip portions configured such that, with the first and second vapor-tight light modules being adjacent, the mounting strip portions are simultaneously received in the mounting channels of both the first and second vapor-tight light modules. Advantageously, with the subject invention, fully enclosed vapor-tight light modules may be provided at shorter lengths which are connected by the coupling to provide a fixture comparable in length to prior-art vapor-tight light fixtures.Type: GrantFiled: July 5, 2018Date of Patent: January 1, 2019Assignee: MAXLITE, Inc.Inventors: Ramesh Raghavan, Jun Xiang
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Patent number: 9859177Abstract: Aspects of the present disclosure include methods and test structures for an intermediate metal level of an integrated circuit (IC). A method according to the present disclosure can include: fabricating a first plurality of metal levels including an intermediate metal level of an IC structure, the intermediate metal level being one of a plurality of metal levels in the IC structure other than a capping metal level of the IC structure; performing a first functional test on a first circuit positioned within the intermediate metal level; fabricating a second plurality of metal levels after performing the first functional test, the second plurality of metal levels including the capping metal level of the IC structure; and performing a second functional test on a second circuit positioned within the plurality of metal levels, after the fabricating of the capping metal level.Type: GrantFiled: March 7, 2016Date of Patent: January 2, 2018Assignee: GLOBALFOUNDRIES INC.Inventors: Janakiraman Viraraghavan, Ramesh Raghavan, Balaji Jayaraman, Thejas Kempanna, Rajesh R. Tummuru, Toshiaki Kirihata
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Patent number: 9786333Abstract: A multi-time programmable memory (MTPM) memory cell and method of operating. Each MTPM bit cell including a first FET transistor and a second FET transistor having a first common connection, and said second FET transistor and a third FET transistor having a second common connection, said first and second connected FET transistors programmable to store a first bit value, and said second FET and said third connected FET transistors programmable to store a second bit value, wherein said first FET transistor exhibits a low threshold voltage value (LVT), said second FET transistor exhibits an elevated threshold voltage value HVT and said third FET transistor exhibits a threshold value LVT lower than HVT. The MTPM cell enables two bits of information to be stored as default bit values like an electrical fuse. To store opposite bit values, the LVT transistors are programmed such that their threshold voltage is higher than that of HVT.Type: GrantFiled: April 4, 2017Date of Patent: October 10, 2017Assignee: GLOBALFOUNDRIES INC.Inventors: Ramesh Raghavan, Balaji Jayaraman, Janakiraman Viraraghavan, Thejas Kempanna, Rajesh Reddy Tummuru, Toshiaki Kirihata
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Patent number: 9761285Abstract: Approaches for a circuit are provided. The circuit includes a sense amplifier circuit which includes a plurality of transistors enabled by a sense amplifier enable signal to output a first output data line true signal and a second output data line complement signal to a latching circuit, and the latching circuit which includes a primary driver actively driven by the first output data line true signal and a secondary driver actively driven by the second output data line complement signal such that the latching circuit outputs a read global data line.Type: GrantFiled: February 26, 2016Date of Patent: September 12, 2017Assignee: GLOBALFOUNDRIES INC.Inventors: Venkatraghavan Bringivijayaraghavan, Ramesh Raghavan
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Publication number: 20170256468Abstract: Aspects of the present disclosure include methods and test structures for an intermediate metal level of an integrated circuit (IC). A method according to the present disclosure can include: fabricating a first plurality of metal levels including an intermediate metal level of an IC structure, the intermediate metal level being one of a plurality of metal levels in the IC structure other than a capping metal level of the IC structure; performing a first functional test on a first circuit positioned within the intermediate metal level; fabricating a second plurality of metal levels after performing the first functional test, the second plurality of metal levels including the capping metal level of the IC structure; and performing a second functional test on a second circuit positioned within the plurality of metal levels, after the fabricating of the capping metal level.Type: ApplicationFiled: March 7, 2016Publication date: September 7, 2017Inventors: Janakiraman Viraraghavan, Ramesh Raghavan, Balaji Jayaraman, Thejas Kempanna, Rajesh R. Tummuru, Toshiaki Kirihata
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Publication number: 20170249976Abstract: Approaches for a circuit are provided. The circuit includes a sense amplifier circuit which includes a plurality of transistors enabled by a sense amplifier enable signal to output a first output data line true signal and a second output data line complement signal to a latching circuit, and the latching circuit which includes a primary driver actively driven by the first output data line true signal and a secondary driver actively driven by the second output data line complement signal such that the latching circuit outputs a read global data line.Type: ApplicationFiled: February 26, 2016Publication date: August 31, 2017Inventors: Venkatraghavan Bringivijayaraghavan, Ramesh Raghavan
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Patent number: 9721673Abstract: A Multi-Time-Programmable-Memory (MTPM) array architecture, whose structure comprising of having Metal-Oxide-Semiconductor Field-Effect-Transistor (MOSFET) memory elements arranged in a set of twin-pairs coupled by wordlines (WLs), bitlines (BLs) and sourcelines (SLs). More specifically, the use of inactive portions of the MTPM array structure as substitutes for conventional BL write driver areas by utilizing a set of twin-pairs acting in parallel. These substituted twin-pair sets will improve programming efficiency (VGS) and retention (VDS) through a lowering Interconnect (IR) drop and VDS drops at the BL write driver.Type: GrantFiled: November 29, 2016Date of Patent: August 1, 2017Assignee: GLOBALFOUNDRIES INC.Inventors: Ramesh Raghavan, Balaji Jayaraman, Rajesh R. Tummuru, Thejas Kempanna, Janakiraman Viraraghavan
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Publication number: 20170206938Abstract: A multi-time programmable memory (MTPM) memory cell and method of operating. Each MTPM bit cell including a first FET transistor and a second FET transistor having a first common connection, and said second FET transistor and a third FET transistor having a second common connection, said first and second connected FET transistors programmable to store a first bit value, and said second FET and said third connected FET transistors programmable to store a second bit value, wherein said first FET transistor exhibits a low threshold voltage value (LVT), said second FET transistor exhibits an elevated threshold voltage value HVT and said third FET transistor exhibits a threshold value LVT lower than HVT. The MTPM cell enables two bits of information to be stored as default bit values like an electrical fuse. To store opposite bit values, the LVT transistors are programmed such that their threshold voltage is higher than that of HVT.Type: ApplicationFiled: April 4, 2017Publication date: July 20, 2017Applicant: GLOBALFOUNDRIES INC.Inventors: Ramesh Raghavan, Balaji Jayaraman, Janakiraman Viraraghavan, Thejas Kempanna, Rajesh Reddy Tummuru, Toshiaki Kirihata
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Publication number: 20170162234Abstract: A multi-time programmable memory (MTPM) memory cell and method of operating. Each MTPM bit cell including a first FET transistor and a second FET transistor having a first common connection, and said second FET transistor and a third FET transistor having a second common connection, said first and second connected FET transistors programmable to store a first bit value, and said second FET and said third connected FET transistors programmable to store a second bit value, wherein said first FET transistor exhibits a low threshold voltage value (LVT), said second FET transistor exhibits an elevated threshold voltage value HVT and said third FET transistor exhibits a threshold value LVT lower than HVT. The MTPM cell enables two bits of information to be stored as default bit values like an electrical fuse. To store opposite bit values, the LVT transistors are programmed such that their threshold voltage is higher than that of HVT.Type: ApplicationFiled: December 7, 2015Publication date: June 8, 2017Applicant: GLOBALFOUNDRIES INC.Inventors: Ramesh Raghavan, Balaji Jayaraman, Janakiraman Viraraghavan, Thejas Kempanna, Rajesh Reddy Tummuru, Toshiaki Kirihata
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Patent number: 9659604Abstract: A multi-time programmable memory (MTPM) memory cell and method of operating. Each MTPM bit cell including a first FET transistor and a second FET transistor having a first common connection, and said second FET transistor and a third FET transistor having a second common connection, said first and second connected FET transistors programmable to store a first bit value, and said second FET and said third connected FET transistors programmable to store a second bit value, wherein said first FET transistor exhibits a low threshold voltage value (LVT), said second FET transistor exhibits an elevated threshold voltage value HVT and said third FET transistor exhibits a threshold value LVT lower than HVT. The MTPM cell enables two bits of information to be stored as default bit values like an electrical fuse. To store opposite bit values, the LVT transistors are programmed such that their threshold voltage is higher than that of HVT.Type: GrantFiled: December 7, 2015Date of Patent: May 23, 2017Assignee: GLOBALFOUNDRIES INC.Inventors: Ramesh Raghavan, Balaji Jayaraman, Janakiraman Viraraghavan, Thejas Kempanna, Rajesh Reddy Tummuru, Toshiaki Kirihata
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Patent number: 9589658Abstract: Approaches for a memory including a cell array are provided. The memory includes a first device of the cell array which is connected to a bitline and a node and controlled by a word line, and a second device of the cell array which comprises a third device which is connected to a source line and the node and controlled by the word line and a fourth device which is connected between the word line and the node. In the memory, in response to another word line in the cell array being activated and the word line not being activated to keep the first device in an unprogrammed state, the third device isolates and floats the node such that a voltage level of a gate to source of the first device is clamped down by the fourth device to a voltage level around zero volts.Type: GrantFiled: August 18, 2015Date of Patent: March 7, 2017Assignee: GLOBALFOUNDRIES INC.Inventors: Navin Agarwal, Aditya S. Auyisetty, Balaji Jayaraman, Thejas Kempanna, Toshiaki Kirihata, Ramesh Raghavan, Krishnan S. Rengarajan, Rajesh R. Tummuru, Jay M. Shah, Janakiraman Viraraghavan
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Publication number: 20170053705Abstract: Approaches for a memory including a cell array are provided. The memory includes a first device of the cell array which is connected to a bitline and a node and controlled by a word line, and a second device of the cell array which comprises a third device which is connected to a source line and the node and controlled by the word line and a fourth device which is connected between the word line and the node. In the memory, in response to another word line in the cell array being activated and the word line not being activated to keep the first device in an unprogrammed state, the third device isolates and floats the node such that a voltage level of a gate to source of the first device is clamped down by the fourth device to a voltage level around zero volts.Type: ApplicationFiled: August 18, 2015Publication date: February 23, 2017Inventors: Navin AGARWAL, Aditya S. AUYISETTY, Balaji JAYARAMAN, Thejas KEMPANNA, Toshiaki KIRIHATA, Ramesh RAGHAVAN, Krishnan S. RENGARAJAN, Rajesh R. TUMMURU, Jay M. SHAH, Janakiraman VIRARAGHAVAN
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Publication number: 20160305635Abstract: A bracket for use with a recessed light fixture includes a side wall. A first bendable tab is positioned in the side wall. A second bendable tab is positioned in the side wall, the second tab being offset from the first tab. A retainer extends from the side wall.Type: ApplicationFiled: April 18, 2016Publication date: October 20, 2016Inventors: Nancy R. Stathes, Federico Collado, Ramesh Raghavan, Shailesh Naik
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Patent number: 9460760Abstract: A system and method of operating a twin-transistor single bit multi-time programmable memory cell to provide a high gain, sensing scheme for small signals. The memory cell includes a pair of a first transistor and a second transistor providing a differential signal output. The first transistor of the memory cell couples a first circuit leg having a first current source load transistor and the second transistor couples a second circuit leg having a second current source load transistor. A programmed value is represented by a voltage threshold shift in one of the first or second transistors. A feedback circuit receives one of: a first signal or a second signal of the differential signals, and generates, in response, a feedback signal which is simultaneously applied to bias each current source load transistor in each the first and second circuit legs to amplify a voltage differential between the differential signal outputs.Type: GrantFiled: January 23, 2015Date of Patent: October 4, 2016Assignee: GLOBALFOUNDRIES INC.Inventors: Balaji Jayaraman, Thejas Kempanna, Toshiaki Kirihata, Ramesh Raghavan, Krishnan S. Rengarajan, Rajesh R. Tummuru
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Publication number: 20160217832Abstract: A system and method of operating a twin-transistor single bit multi-time programmable memory cell to provide a high gain, sensing scheme for small signals. The memory cell includes a pair of a first transistor and a second transistor providing a differential signal output. The first transistor of the memory cell couples a first circuit leg having a first current source load transistor and the second transistor couples a second circuit leg having a second current source load transistor. A programmed value is represented by a voltage threshold shift in one of the first or second transistors. A feedback circuit receives one of: a first signal or a second signal of the differential signals, and generates, in response, a feedback signal which is simultaneously applied to bias each current source load transistor in each the first and second circuit legs to amplify a voltage differential between the differential signal outputs.Type: ApplicationFiled: January 23, 2015Publication date: July 28, 2016Applicant: GLOBALFOUNDRIES INC.Inventors: Balaji Jayaraman, Thejas Kempanna, Toshiaki Kirihata, Ramesh Raghavan, Krishnan S. Rengarajan, Rajesh R. Tummuru
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Publication number: 20150276184Abstract: A light fixture assembly includes a light source, a reflector and a shield. The light source emits a beam of light. The reflector directs at least a portion of the beam of light emitted from the light source. The shield is positioned in the reflector to intercept at least a portion of the light emitted from the light source.Type: ApplicationFiled: March 30, 2015Publication date: October 1, 2015Inventors: Nancy R. Stathes, Federico Collado, JR., Ramesh Raghavan