Abstract: Methods and devices for epitaxially growing boron doped silicon germanium layers. The layers may be used, for example, as a p-type source and/or drain regions in field effect transistors.

Abstract: Methods and systems for selectively forming phosphorus-doped epitaxial material. The methods can be used to selectively form the phosphorus-doped epitaxial material within a gap from the bottom upward. Exemplary methods can be used to, for example, form source and/or drain regions in field effect transistor devices, such as in gate-all-around field effect transistor devices.

Abstract: A method for forming a Si-comprising epitaxial layer selectively on a substrate is disclosed. Embodiments of the presently described method comprise performing a cyclic deposition and etch processes, thereby forming selectively the Si-comprising epitaxial layer. The described method may help to form source/drain regions of field effect transistors in a bottom-up manner.

Abstract: A method for forming an epitaxial stack on a plurality of substrates comprises providing a plurality of substrates to a process chamber and executing deposition cycles, wherein each deposition cycle comprises a first deposition pulse and a second deposition pulse. The epitaxial stack comprises a first epitaxial layer stacked alternatingly and repeatedly with a second epitaxial layer, the second epitaxial layer being different from the first epitaxial layer. The first deposition pulse comprises a provision of a first reaction gas mixture to the process chamber, thereby forming the first epitaxial layer having a first native lattice parameter. The second deposition pulse comprises a provision of a second reaction gas mixture to the process chamber, thereby forming the second epitaxial layer having a second native lattice parameter, wherein the first native lattice parameter lies in a range within 1.5% larger than and 0.9% smaller than the second native lattice parameter.

Abstract: Methods and systems for forming a p-type doped silicon germanium layer. The p-type doped silicon germanium layer can include silicon, germanium, gallium, and, in at least some cases, indium.

Abstract: Methods and systems for selectively forming crystalline boron-doped silicon germanium on a surface of a substrate. The methods can be used to selectively form the boron-doped silicon germanium within a gap from the bottom upward. Exemplary methods can be used to, for example, form source and/or drain regions in field effect transistor devices, such as in gate-all-around field effect transistor devices.

Abstract: Some examples herein provide a method of forming a doped silicon germanium layer. The method may include simultaneously exposing a substrate to (a) a silicon precursor, (b), a germanium precursor, (c) a boron precursor, and (d) a heteroleptic gallium precursor. The heteroleptic gallium precursor may include (i) at least one straight chain alkyl group in which a terminal carbon is directly bonded to gallium, and (ii) at least one tertiary alkyl group in which a tertiary carbon is directly bonded to gallium. The method may include reacting the silicon precursor, the germanium precursor, the boron precursor, and the heteroleptic gallium precursor to form a silicon germanium layer on the substrate that is doped with boron and gallium.

Abstract: Methods and devices for low-temperature deposition of phosphorous-doped silicon layers. Disilane is used as a silicon precursor, and nitrogen or a noble gas is used as a carrier gas. Phosphine is a suitable phosphorous precursor.

Abstract: Methods for forming structures that include forming a heteroepitaxial layer on a substrate are disclosed. The presently disclosed methods comprise epitaxially forming a buffer layer on the substrate. The substrate has a substrate composition. The buffer layer has a buffer layer composition. The buffer layer composition is substantially identical to the substrate composition. The presently disclosed methods further comprise epitaxially forming a heteroepitaxial layer on the buffer layer. The heteroepitaxial layer has a heteroepitaxial layer composition which is different from the substrate composition.

Abstract: A method and a wafer processing furnace for forming an epitaxial stack on a plurality of substrates is provided. In a preferred embodiment, the method comprises providing the plurality of substrates to a process chamber. A plurality of deposition cycles is executed, thereby forming the epitaxial stack on the plurality of substrates. The epitaxial stack comprises a plurality of epitaxial pairs, wherein the epitaxial pairs each comprises a first epitaxial layer and a second epitaxial layer, the second epitaxial layer being different from the first epitaxial layer. Each deposition cycle comprises a first deposition pulse and a second deposition pulse. The first deposition pulse comprises a provision of a first reaction gas mixture to the process chamber, thereby forming the first epitaxial layer. The second deposition pulse comprises a provision of a second reaction gas mixture to the process chamber, thereby forming the second epitaxial layer.

Abstract: Methods for forming structures that include a layer comprising silicon germanium are disclosed. Exemplary embodiments of the disclosure provide improved methods of forming a transition layer on the layer comprising silicon germanium that can mitigate any formation of an interface layer between the layer comprising silicon germanium and a subsequently formed layer comprising silicon.

Abstract: Methods and systems for depositing material, such as doped semiconductor material, are disclosed. An exemplary method includes providing a substrate, forming a first doped semiconductor layer overlying the substrate, and forming a second doped semiconductor layer overlying the first doped semiconductor layer, wherein the first doped semiconductor layer comprises a first dopant and a second dopant, and wherein the second doped semiconductor layer comprises the first dopant. Structures and devices formed using the methods and systems for performing the methods are also disclosed.

Abstract: A method for selectively forming an n-type doped material on a surface of a substrate is disclosed. A system for performing the method and structures and devices formed using the method are also disclosed.

Abstract: Methods and systems for selectively depositing material, such as doped semiconductor material, are disclosed. An exemplary method includes providing a substrate, comprising a first area comprising a first material and a second area comprising a second material, selectively depositing a first doped semiconductor layer overlying the first material relative to the second material and selectively depositing a second doped semiconductor layer overlying the first doped semiconductor layer relative to the second material.

Abstract: Methods and systems for depositing material, such as doped semiconductor material, are disclosed. An exemplary method includes providing a substrate, forming a first doped semiconductor layer overlying the substrate, and forming a second doped semiconductor layer overlying the first doped semiconductor layer, wherein the first doped semiconductor layer comprises a first dopant and a second dopant, and wherein the second doped semiconductor layer comprises the first dopant. Structures and devices formed using the methods and systems for performing the methods are also disclosed.

Abstract: Methods and systems for selectively depositing a p-type doped silicon germanium layer and structures and devices including a p-type doped silicon germanium layer are disclosed. An exemplary method includes providing a substrate, comprising a surface comprising a first area comprising a first material and a second area comprising a second material, within a reaction chamber; depositing a p-type doped silicon germanium layer overlying the surface, the p-type doped silicon germanium layer comprising gallium; and depositing a cap layer overlying the p-type doped silicon germanium layer. The method can further include an etch step to remove the cap layer and the p-type doped silicon germanium layer overlying the second material.

Abstract: A method of forming a structure includes supporting a substrate within a reaction chamber of a semiconductor processing system, the substrate having a recess with a bottom surface and a sidewall surface extending upwards from the bottom surface of the recess. A film is deposited within the recess and onto the bottom surface and the sidewall surface of the recess, the film having a bottom segment overlaying the bottom surface of the recess and a sidewall segment deposited onto the sidewall surface of the recess. The sidewall segment of the film is removed while at least a portion bottom segment of the film is retained within the recess, the sidewall segment of the film removed from the sidewall surface more rapidly than removing the bottom segment of the film from the bottom surface of the recess. Semiconductor processing systems and structures formed using the method are also described.

Abstract: Methods and devices for epitaxially growing boron doped silicon germanium layers. The layers may be used, for example, as a p-type source and/or drain regions in field effect transistors.

Abstract: Methods and systems for selectively depositing a p-type doped silicon germanium layer and structures and devices including a p-type doped silicon germanium layer are disclosed. An exemplary method includes providing a substrate, comprising a surface comprising a first area comprising a first material and a second area comprising a second material, within a reaction chamber; depositing a p-type doped silicon germanium layer overlying the surface, the p-type doped silicon germanium layer comprising gallium; and depositing a cap layer overlying the p-type doped silicon germanium layer. The method can further include an etch step to remove the cap layer and the p-type doped silicon germanium layer overlying the second material.

Abstract: Methods and devices for epitaxially growing boron doped silicon germanium layers. The layers may be used, for example, as a p-type source and/or drain regions in field effect transistors.