Abstract: A source switching device in a switching system receives information measured by a target switching device in the switching system. The information is indicative of an amount of data received in a given amount of time by the target switching device via each of two or more first links coupled to the target switching device. The source switching device determines, based at least in part on the information received from the target device, a path, from among multiple paths from the source switching device to the target switching device, for transmission of a packet flow directed to the target switching device. The source switching device transmits, via the determined path for transmission of the packet flow to the target device, one or more packets belonging to the packet flow.

Abstract: A network device includes a receive processor configured to store, in a packet memory, a payload of a packet received from a communication network. The network device also includes a packet processor configured to modify one or more fields of a header of the packet to generate a modified header, perform egress classification of the packet based on the modified header, and store the modified header in the packet memory. The network device further includes a transmit processor configured to transmit the packet in accordance with the egress classification. The transmit processor is configured to, in response to a decision that the packet is to be transmitted from the network device, generate a transmit packet from the payload retrieved from the packet memory and the modified header retrieved from the packet memory and cause the transmit packet to be transmitted to a destination in the communication network.

Abstract: A packet processor of a network device receives packets ingressing from a plurality of network links via a plurality of network ports of the network device. The packet processor buffers the packets in an internal packet memory in a plurality of queues, including a first queue. In response to the packet processor detecting congestion in the internal packet memory, the packet processor selectively forwards a group of multiple packets in the first queue from the internal packet memory to a first port, among one or more ports coupled to one or more external memories, to transfer the group of multiple packets to a first external memory that is coupled to the first port so that the first queue is stored across the internal packet memory and the first external packet memory.

Abstract: A search engine of a network device performs a lookup based on packet information associated with a packet being processed using a plurality of packet processing applications. The lookup includes one or more accesses to a lookup table that includes a plurality of interleaved entries associated with different ones of the packet processing applications. For each access, the search engine generates a search key to include at least a search string generated based on the packet information and an application identifier indicating a packet processing application for which the lookup is being performed, identifies an entry based on the search key, determines whether the search key matches search information in the identified entry, and when the search key matches the search information in the identified entry, identifies an action to be performed by the packet processor in connection with processing the packet by the packet processing application.

Abstract: A network device includes a packet processor that: determines at least one egress port via which a received packet is to be transmitted by the network device; modifies one or more fields in a header of the packet to generate a modified header; determines, based at least in part on the modified header, whether the packet a) is to be transmitted or b) is to be discarded; and stores the modified header in a packet memory. In response to the determination that the packet is to be transmitted, a transmit processor of the network device: retrieves a payload of the packet from the packet memory; retrieves the modified header from the packet memory; generates a transmit packet at least by combining the payload of the packet with the modified header; and transmits the transmit packet via the determined at least one egress port of the network device.

Abstract: In a network switching system that comprises a plurality of interconnected network devices, a first network device transmits one or more first packets via a first network interface of the first network device, the one or more first packets belonging to a packet flow. The first network device receives a message that indicates congestion corresponding to the packet flow within the network switching system. In response to the message, the first network device selects a second network interface of the first network device for transmitting one or more second packets that belong to the packet flow. After receiving the message, the first network device transmits the one or more second packets via the second network interface of the first network device.

Abstract: A network device includes a rate measurement circuit that is configured to measure respective egress rates at which respective data is being transmitted via respective ports associated with the network device. A marking ratio determination circuit is configured to select respective marking ratios based on respective measured egress rates, the marking ratios for marking packets to be transmitted via the respective ports to indicate respective levels of congestion corresponding to the respective ports. Different marking ratios correspond to different measured egress rates. A packet editor circuit is configured to mark selected packets to be transmitted via respective ports according to the respective selected marking ratios. The respective selected marking ratios indicate to other communication devices that respective network paths via which the selected packets travelled experienced congestion, and the respective marking ratios indicate respective levels of congestion.

Abstract: A network device comprises a network interface configured to transmit packets via a network link, and timestamp circuitry configured to modify a packet that is to be transmitted by the network interface circuitry by embedding a future timestamp in the packet. The future timestamp corresponds to a transmit time at which the packet is to be transmitted by the network interface circuitry, and the transmit time occurs after the timestamp circuitry embeds the timestamp in the packet. Time gating circuitry is configured to i) receive the packet, ii) determine when a current time indicated by a clock circuit reaches the transmit time, iii) hold the packet from proceeding to the network interface circuitry prior to the current time reaching the transmit time, and iv) release the packet in response to the current time reaching the transmit time.

Abstract: A network device transfers packets from a packet memory to one or more network interfaces for transmission by the one or more network interfaces. The transferring of packets includes transferring the packets via one or more respective transmit data paths that correspond to one or more respective network interfaces. The network device measures one or more respective amounts of time required to transmit respective packet data within the one or more respective transmit data paths. The network device uses the one or more respective measured amounts of time to determine when to start transfer of packets from the packet memory to the one or more network interfaces via the one or more respective transmit data paths.

Abstract: A network device includes a first queue for queueing express packets and a second queue for queueing preemptable packets that are to be transmitted via a network interface of the network device. The network device also includes a transmit controller that receives a packet directed to the first queue and determines whether the packet is a type of packet that requires transmission at a specific transmit time from the network interface of the network device. In response to determining that the packet is a type of packet that requires transmission at a specific transmit time, the transmit controller suspends an ongoing transmission of a preemptable packet from the second queue that would prevent transmission of the packet from the first queue at the specific transmit time via the network interface and causes the packet in the first queue to be transmitted at the specific transmit time via the network interface.

Abstract: A packet processor of a network device receives packets ingressing from a plurality of network links via a plurality of network ports of the network device. The packet processor buffers the packets in an internal packet memory in a plurality of queues, including a first queue. In response to the packet processor detecting congestion in the internal packet memory, the packet processor selectively forwards a group of multiple packets in the first queue from the internal packet memory to a first port, among one or more ports coupled to one or more external memories, to transfer the group of multiple packets to a first external memory that is coupled to the first port so that the first queue is stored across the internal packet memory and the first external packet memory.

Abstract: A packet group processor of a network device defines groups of packets among packets that are being processed by the network device, each of at least some of the groups of packets defining a respective group of at least two different packets. Each group includes one or more packets to be transmitted via a respective same network interface. A transmit processor makes a single transmit decision that a particular group of at least two packets is to be transmitted via a corresponding network interface, and in response to the single transmit decision, transfers the particular group of at least two packets to the corresponding network interface for transmission.

Abstract: At least a packet header of a packet received by a network device is provided to a programmable header alteration engine that includes a hardware input processor implemented in hardware and a programmable header alteration processor configured to execute computer readable instructions stored in a program memory. The hardware input processor determines whether the packet header is to be provided to a processing path coupled to the programmable header alteration processor or to be diverted to a bypass path that bypasses the programmable header alteration processor, and the packet header is provided to the processing path or to the bypass path based on the determination. The packet header is selectively i) processed by the programmable header alteration processor when the packet header is provided to the processing path and ii) not processed by the programmable header alteration processor when the packet header is provided to the bypass path.

Abstract: Packets to be transmitted from a network device are buffered in queues in a first packet memory. In response to detecting congestion in a queue in the first packet memory, groups of multiple packets are transferred from the first packet memory to a second packet memory, the second packet memory configured to buffer a portion of traffic bandwidth supported by the network device. Prior to transmission of the packets among the one or more groups of multiple packets from the network device, packets among the one or more groups of multiple packets are transferred from the second packet memory back to the first packet memory. The packets transferred from the second packet memory back to the first packet memory are retrieved from the first packet memory and are forwarded to one or more network ports for transmission of the packets from the network device.

Abstract: A network device includes a transmit buffer from which data is transmitted to a network, and a packet buffer from which data chunks are transmitted to the transmit buffer in response to read requests. The packet buffer has a maximum read latency from receipt of a read request to transmission of a responsive data chunk, and receives read requests including a read request for a first data chunk of a network packet and a plurality of additional read requests for additional data chunks of the network packet. A latency timer monitors elapsed time from receipt of the first read request, and outputs a latency signal when the elapsed time reaches the first maximum read latency. Transmission logic waits until the elapsed time equals the first maximum read latency, and then transmits the first data chunk from the transmit buffer, without regard to a fill level of the transmit buffer.

Abstract: Schedules that indicate when time gates of a network device are to permit transfer of packet data are stored in a memory. Control circuitry repeatedly identifies initial positions in the schedules corresponding to times when the schedules are accessed in a background procedure. The control circuitry uses the identified initial positions to identify updated positions in the schedules that correspond to events when control of the time gates is needed, and uses scheduling information at the updated positions in the schedules to selectively transfer packet data to components of the network device using the time gates.

Abstract: At least a packet header of a packet received by a network device is provided to a programmable header alteration engine that includes a hardware input processor implemented in hardware and a programmable header alteration processor configured to execute computer readable instructions stored in a program memory. The hardware input processor determines whether the packet header is to be provided to a processing path coupled to the programmable header alteration processor or to be diverted to a bypass path that bypasses the programmable header alteration processor, and the packet header is provided to the processing path or to the bypass path based on the determination. The packet header is selectively i) processed by the programmable header alteration processor when the packet header is provided to the processing path and ii) not processed by the programmable header alteration processor when the packet header is provided to the bypass path.

Abstract: A network device for a communications network includes a port configured to transmit data to the network at a maximum transmit data rate. The device also includes a transmit buffer configured to buffer data units that are ready for transmission to the network, and a packet buffer configured to buffer data units before the data units are ready for transmission. The packet buffer is configured to output data units at a maximum packet buffer transmission rate faster than the maximum transmit data rate. The device includes a rate controller configured to control a transmission rate of data from the packet buffer to the transmit buffer so that averaged over a period, the transmission rate from the packet buffer to the transmit buffer is at most equal to the maximum transmit data rate, while allowing the transmission rate, at one or more time intervals, to exceed the maximum transmit data rate.

Abstract: A network device comprises time measurement units configured to measure receipt times and transmit times of packets received/transmitted via network interfaces. One or more memories store configuration information that indicates certain network interface pairs and/or certain packet flows that are enabled for latency measurement. A packet processor includes a latency monitoring trigger unit configured to select, using the configuration information, packets that are forwarded between the certain network interface pairs and/or that belong to the certain packet flows for latency monitoring.

Abstract: Flow state information that is stored in a first memory among a plurality of memories for maintaining flow state information at a network device is updated based on packets ingressing the network device. The memories are arranged in a hierarchical arrangement in which memories at progressively higher levels of hierarchy are configured to maintain flow state information corresponding to progressively larger sets of flows processed by the network device. When it is determined that a fullness level of the first memory exceeds a first threshold, flow state information associated with at least one flow, among a first set of flows for which flow state information is currently being maintained in the first memory, is transferred from the first memory to a second memory, the second memory being at a higher hierarchical level than the first memory. A new flow is instantiated in space freed up in the first memory.