Abstract: An integrated receiver decoder for receiving digitally modulated signals from a satellite is disclosed. The receiver includes a tuner, a demodulator, a low-noise block (LNB) controller, a voltage controller and a voltage selector implemented within a single monolithic integrated circuit device. The tuner amplifies and filters satellite signals received from a directional receiver antenna. The demodulator, which is coupled to the tuner, demodulates and decodes the received satellite signals. The LNB controller generates and detects a modulated tone to facilitate communications between the receiver and an LNB feed attached to the directional receiver antenna. The voltage selector directs the voltage controller to provide a control signal for controlling an external voltage regulator to generate a variable voltage to the LNB feed attached to the directional receiver antenna.

Abstract: A multi-protocol modulator capable of supporting two or more different modes of operation, each mode of operation corresponding to a different type of modulation, comprises an m-level phase shift keying (m-PSK) modulator which receives a serial input data stream and maps data contained therein into a constellation including m equidistant phases in accordance with a predetermined mapping scheme. The m-PSK modulator is shared by at least two different modulation protocols by allowing the mapping scheme to be selectively changed depending upon the modulation protocol used. The multi-protocol modulator further includes a phase rotator operatively coupled to the output of the m-PSK modulator. The phase rotator selectively rotates the phase of the m-PSK signal by a predetermined phase rotation value. The phase rotator is shared by the two or more modulation protocols by allowing the phase rotation value to be selectively modified depending upon the modulation protocol used.

Abstract: communication terminal (710) includes a coder (722, 724) receiving an input signal and having an output terminal for providing a coded signal; an upconverter core (100) having an input terminal for receiving a first signal having predetermined spectral content at an input frequency and an output terminal for providing an output signal having substantially the predetermined spectral content at a higher frequency using a local oscillator signal having a carrier frequency; an electrical measurement circuit having an input terminal coupled to the output terminal of the upconverter core (100), and an output terminal for providing a first offset correction signal representative of a power of the output signal at the carrier frequency; and a summing device (406) having a positive input terminal for receiving the coded signal, a negative input terminal coupled to the output terminal of the electrical measurement circuit, and an output terminal coupled to the input terminal of the upconverter core (100).

Abstract: An RF upconverter (400, 500) includes an upconverter core (100), an electrical measurement circuit, and a summing device (406). The upconverter core (100) has an input terminal for receiving a first signal having predetermined spectral content at an input frequency and an output terminal for providing an output signal having substantially the predetermined spectral content at a higher frequency using a local oscillator signal having a carrier frequency. The electrical measurement circuit has an input terminal coupled to the output terminal of the upconverter core (100), and an output terminal for providing a first offset correction signal representative of a power of the output signal at the carrier frequency. The summing device (406) has a positive input terminal for receiving a first input signal, a negative input terminal coupled to the output terminal of the electrical measurement circuit, and an output terminal coupled to the input terminal of the upconverter core (100) for providing the first signal.

Abstract: In various embodiments, the present invention includes an apparatus that includes a receiver having multiple tuners. Such multiple tuners may each receive a signal channel using multiple local oscillator (LO) frequencies that do not interfere with each other. In certain embodiments, each tuner may have an associated VCO so that no multiplexer is needed. Also, the present invention includes methods to determine a minimum bandwidth for baseband filters of the receiver and an LO step frequency between different possible LO frequencies.

Abstract: Integrated multiple tuner architectures and associated methods are disclosed that utilize frequency isolated local oscillators (LO). These architectures utilize dividers and multipliers within the signal paths for the local oscillator mixing signals to reduce interference among the multiple local oscillators operating on a single integrated circuit. A multiple tuner direct-down-conversion (DDC) receiver and a multiple tuner intermediate frequency (IF) receiver are provided as example embodiments. And an example integrated multi-tuner satellite receiver is also described.

Abstract: Methods and architectures for tuning bandpass analog-to-digital converters (ADCs) are disclosed that can be used, for example, with receiver architectures and associated methods that are also disclosed. The notch of the bandpass ADC can be tuned to the desired channel frequency by adjusting the notch to reduce noise energy in the output signal through a feedback process that adjusts the tuning signal. In addition, a master-slave approach can be implemented to tune a tunable bandpass filter configured as a slave circuit based upon the tuning adjustments made to the master bandpass ADC circuit. In addition, receiver architectures and associated methods are disclosed that utilize coarse analog tune circuitry to provide initial analog coarse tuning of desired channels within a received spectrum signal, such as a set-top box signal spectrum for satellite communications.

Abstract: Methods and architectures for tuning bandpass analog-to-digital converters (ADCs) are disclosed that can be used, for example, with receiver architectures and associated methods that are also disclosed. The notch of the bandpass ADC can be tuned to the desired channel frequency by adjusting the notch to reduce noise energy in the output signal through a feedback process that adjusts the tuning signal. In addition, a master-slave approach can be implemented to tune a tunable bandpass filter configured as a slave circuit based upon the tuning adjustments made to the master bandpass ADC circuit. In addition, receiver architectures and associated methods are disclosed that utilize coarse analog tune circuitry to provide initial analog coarse tuning of desired channels within a received spectrum signal, such as a set-top box signal spectrum for satellite communications.

Abstract: Multi-tuner receiver architectures and associated methods are disclosed that provide initial analog coarse tuning of desired channels within a received signal spectrum, such as transponder channels within a set-top box signal spectrum for satellite communications. These multi-tuner satellite receiver architectures provide significant advantages over prior direct down-conversion (DDC) architectures and low intermediate-frequency (IF) architectures, particularly where two tuners are desired on the same integrated circuit. Rather than using a low-IF frequency or directly converting the desired channel frequency to DC, initial coarse tuning provided by analog coarse tuning circuitry allows for a conversion to a frequency range around DC. This coarse tuning circuitry can be implemented, for example, using a large-step local oscillator (LO) that provides a coarse tune analog mixing signal.

Abstract: Receiver architectures and associated methods are disclosed that provide initial analog coarse tuning of desired channels within a received signal spectrum, such as a set-top box signal spectrum for satellite communications. These architectures provide significant advantages over prior direct down-conversion (DDC) architectures and low intermediate-frequency (IF) architectures, particularly where two tuners are desired on the same integrated circuit. Rather than using a low-IF frequency or directly converting the desired channel frequency to DC, initial coarse tuning provided by analog coarse tuning circuitry allows for a conversion to a frequency range around DC. This coarse tuning circuitry can be implemented, for example, using a large-step local oscillator (LO) that provides a coarse tune analog mixing signal.

Abstract: A digital-to-analog converter circuit for a subscriber line analog front end includes a differential amplifier, switch circuitry, and first and second current steering digital-to-analog converters (DAC), each DAC having a first and second output forming a differential DAC output. The switch circuitry couples the differential output of at most a selected one of the first and second DACs to a pair of switch nodes. When the differential output of the selected DAC is coupled to the pair of switch nodes, the differential output of the other DAC is shorted. A differential input of the differential amplifier is communicatively coupled to the pair of switch nodes. A differential output of the differential amplifier is coupled to drive a tip line and a ring line of a subscriber line. In various embodiments, the DACs, switch circuitry, and differential amplifier reside on the same semiconductor substrate.

Abstract: A digital-to-analog conversion circuit includes first and second DACs. Switch circuitry couples a selected output of only one of the DACs to an output node at any given time. In one embodiment, a second output of the first DAC is coupled to the first output of the second DAC at a common node. The first output of the first DAC is coupled to a first switch node and a second output of the second DAC is coupled to a second switch node. A first switch couples the common node to the first switch node in response to a first switch signal. A second switch couples the common node to the second switch node in response to a second switch signal. The switch signals ensure that the common node is coupled through the first and second switches to only one of the first and second switch nodes at any given time.

Abstract: A digital-to-analog conversion circuit includes first and second DACs. Switch circuitry couples a selected output of only one of the DACs to an output node at any given time. In one embodiment, a second output of the first DAC is coupled to the first output of the second DAC at a common node. The first output of the first DAC is coupled to a first switch node and a second output of the second DAC is coupled to a second switch node. A first switch couples the common node to the first switch node in response to a first switch signal. A second switch couples the common node to the second switch node in response to a second switch signal. The switch signals ensure that the common node is coupled through the first and second switches to only one of the first and second switch nodes at any given time.

Abstract: A transmit portion of a WB-CDMA transceiver generates one or more spread data streams having values represented by a single bit, allowing for filtering of spread and combined data streams with a root raised cosine (RRC) filter employing single-bit multipliers. The RRC filter is a digital filter that i) employs multiplication of two values in which the length of at least one value is one bit; ii) is preferably implemented with muxs or a simple logic operator; and iii) may employ upsampling and modulation encoding of filter coefficients to reduce the coefficient length to, for example, one bit. The RRC filter may be an FIR filter having either one-bit or multi-bit coefficients, and apply RRC filtering to a spread user stream either before or after the spread user streams are combined. For some implementations, RRC filters are employed to filter each spread user stream prior to combining several processed user steams.

Abstract: A multi-protocol modulator capable of supporting two or more different modes of operation, each mode of operation corresponding to a different type of modulation, comprises an m-level phase shift keying (m-PSK) modulator which receives a serial input data stream and maps data contained therein into a constellation including m equidistant phases in accordance with a predetermined mapping scheme. The m-PSK modulator is shared by at least two different modulation protocols by allowing the mapping scheme to be selectively changed depending upon the modulation protocol used. The multi-protocol modulator further includes a phase rotator operatively coupled to the output of the m-PSK modulator. The phase rotator selectively rotates the phase of the m-PSK signal by a predetermined phase rotation value. The phase rotator is shared by the two or more modulation protocols by allowing the phase rotation value to be selectively modified depending upon the modulation protocol used.

Abstract: A signal processing system includes a main digital-to-analog converter (DAC) for receiving a digital baseband signal and converting the digital signal into an analog signal. Also included in the system is a connection circuit for receiving the analog signal, and output terminal, and an analog filter coupled between the connection circuit and the output terminal for filtering the analog signal. The system includes a calibration circuit coupled between the connection circuit and the output terminal for setting an offset voltage level. The calibration circuit includes (a) an approximation circuit coupled to the output terminal and operable during a calibration mode to determine the offset voltage level and store the offset voltage level as a digital offset signal and (b) an offset DAC coupled between the connection circuit and the approximation circuit for converting the digital offset signal into the offset voltage level.

Abstract: A method and apparatus for generating two disparate frequency reference signals using a single phase locked loop. The circuit includes a local oscillator for generating a reference signal and a phase comparator for comparing the reference signal with a feedback signal. The output of the phase comparator is converted to a first one of the desired output frequencies by a voltage controlled oscillator. That signal is also fed to a variable frequency divider circuit under control of a &Sgr;/&Dgr; converter which generates a lower frequency signal without creating a secondary frequency tone. The lower frequency signal is the second of the output frequencies. This signal also is fed back to the second input of the phase comparator through a fixed frequency divider.

Abstract: A digital filter receives signals from each stage of a MASH delta-sigma modulator and filters noise components from the signals prior to combination as a single sequence of values decimation. Each stage of the MASH delta-sigma modulator provides an output sequence of one-bit, binary values, which are then filtered to remove high-order, out of band quantization noise. After filtering, the output sequences are then combined through a cascade-combiner, which may be similar to the pre-processing stage of a MASH delta-sigma modulator architecture. The digital filter processes signals of each stage separately. Consequently, the digital filter does not perform multiplication of two, multi-bit values. Multiplication of two values, the first of which is a one-bit, binary value, may be implemented with a multiplexer selecting either the second value or a zero value based on the first one-bit, binary value (i.e., logic 1 or 0, respectively).

Abstract: A mixed signal integrated circuit board having decreased sensitivity of analog circuitry to digital circuitry noise is disclosed. In the mixed-signal integrated board of the present invention, a new (second) analog ground is created. This new analog ground is not limited by the manufacturing specification of connectivity to the substrate of the circuit board and is thereby free of transient noise generated by digital components on the board. In a mixed-signal integrated circuit board of the present invention, the new analog ground becomes the preferred ground and is utilized in many sensitive analog applications including voltage and current measurements. The new analog ground is easy to create as it does not involved complicated circuitry. The new analog ground may be created even after the initial circuit schematics has been created.

Abstract: A circuit and method for detecting mobile ion contamination in a semiconductor device. The circuit uses two transistor structures on the same silicon chip as the circuit being tested to detect the presence (or absence) of mobile ions. The test includes imposing conditions on the silicon chip that may cause any mobile ions present therein to move within the structure. By measuring electrical parameters, such as a band gap voltage, across the transistors before and after the imposition of such conditions, a reliable indication of the presence or absence of mobile ions can be obtained.