Patents by Inventor Raminderpal Singh
Raminderpal Singh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8594826Abstract: A method, a system and a computer program product suitable for use in a manufacturing environment comprising a multiplicity of nominally identical independent tools. A computing device generates a multi dimensional array of process trace data derived from at least one of the independent tools, wherein, the array includes data representing a first dimension comprising a list of steps in a manufacturing recipe and data representing a second dimension comprising a list of a set of sensors generating measurements from at least one of the independent tools. The computing device conducts an analysis on at least one preselected subset of the multi dimensional array for the purpose of evaluating at least one operating characteristic of at least one of the independent tools. The computing device presents results of the analysis via a set of hierarchically linked and browseable graphics.Type: GrantFiled: September 10, 2012Date of Patent: November 26, 2013Assignee: International Business Machines CorporationInventors: Ehud Aharoni, Robert J. Baseman, Ramona Kei, Oded Margalit, Kevin Mackey, Michal Rosen-Zvi, Raminderpal Singh, Noam Slonim, Hong Lin, Fateh A. Tipu, Adam D. Ticknor, Timothy M. McCormack
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Publication number: 20130006406Abstract: A method, a system and a computer program product suitable for use in a manufacturing environment comprising a multiplicity of nominally identical independent tools. A computing device generates a multi dimensional array of process trace data derived from at least one of the independent tools, wherein, the array includes data representing a first dimension comprising a list of steps in a manufacturing recipe and data representing a second dimension comprising a list of a set of sensors generating measurements from at least one of the independent tools. The computing device conducts an analysis on at least one preselected subset of the multi dimensional array for the purpose of evaluating at least one operating characteristic of at least one of the independent tools. The computing device presents results of the analysis via a set of hierarchically linked and browseable graphics.Type: ApplicationFiled: September 10, 2012Publication date: January 3, 2013Applicant: International Business Machines CorporationInventors: Ehud Aharoni, Robert J. Baseman, Ramona Kei, Oded Margalit, Kevin Mackey, Michal Rosen-Zvi, Raminderpal Singh, Noam Slomin, Hong Lin, Fateh Ali Tipu, Adam Daniel Ticknor, Timothy M. McCormack
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Patent number: 8285414Abstract: A method and system for evaluating a performance of a semiconductor manufacturing tool while manufacturing microelectronic devices are disclosed. At least one report is generated based on executions of at least one statistical test. The report includes at least one heat map having rows that correspond to sensors, columns that correspond to trace data obtained during recipe steps, and cells at the intersection of the rows and the columns. At least one sensor in the tool obtains trace data of a recipe step while manufacturing at least one microelectronic device. A computing device analyzes the obtained trace data to determine a level of operational significance found in the data and assigns a score to the trace data that indicates a level of operational significance. Then, the computing device places the score in a corresponding cell of the heat map. A user uses the cell for evaluating the tool performance.Type: GrantFiled: March 31, 2009Date of Patent: October 9, 2012Assignee: International Business Machines CorporationInventors: Ehud Aharoni, Robert J. Baseman, Ramona Kei, Oded Margalit, Kevin Mackey, Michal Rosen-Zvi, Raminderpal Singh, Noam Slonim, Hong Lin, Fateh A. Tipu, Adam D. Ticknor, Timothy M. McCormack
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Patent number: 8212332Abstract: A novel and useful apparatus for and method of providing noise isolation between integrated circuit devices on a semiconductor chip. The invention addresses the problem of noise generated by digital switching devices in an integrated circuit chip that may couple through the silicon substrate into sensitive analog circuits (e.g., PLLs, transceivers, ADCs, etc.) causing a significant degradation in performance of the sensitive analog circuits. The invention utilizes a deep trench capacitor (DTCAP) device connected to ground to isolate victim circuits from aggressor noise sources on the same integrated circuit chip. The deep penetration of the capacitor creates a grounded shield deep in the substrate as compared with other prior art shielding techniques.Type: GrantFiled: August 11, 2011Date of Patent: July 3, 2012Assignee: International Business Machines CorporationInventors: Phillip Francis Chapman, David Goren, Rajendran Krishnasamy, Benny Sheinman, Shlomo Shlafman, Raminderpal Singh, Wayne H. Woods
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Publication number: 20110291238Abstract: A novel and useful apparatus for and method of providing noise isolation between integrated circuit devices on a semiconductor chip. The invention addresses the problem of noise generated by digital switching devices in an integrated circuit chip that may couple through the silicon substrate into sensitive analog circuits (e.g., PLLs, transceivers, ADCs, etc.) causing a significant degradation in performance of the sensitive analog circuits. The invention utilizes a deep trench capacitor (DTCAP) device connected to ground to isolate victim circuits from aggressor noise sources on the same integrated circuit chip.Type: ApplicationFiled: August 11, 2011Publication date: December 1, 2011Applicant: International Business Machines CorporationInventors: Phillip Francis Chapman, David Goren, Rajendran Krishnasamy, Benny Sheinman, Shlomo Shlafman, Raminderpal Singh, Wayne H. Woods
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Patent number: 8021941Abstract: A novel and useful apparatus for and method of providing noise isolation between integrated circuit devices on a semiconductor chip. The invention addresses the problem of noise generated by digital switching devices in an integrated circuit chip that may couple through the silicon substrate into sensitive analog circuits (e.g., PLLs, transceivers, ADCs, etc.) causing a significant degradation in performance of the sensitive analog circuits. The invention utilizes a deep trench capacitor (DTCAP) device connected to ground to isolate victim circuits from aggressor noise sources on the same integrated circuit chip. The deep penetration of the capacitor creates a grounded shield deep in the substrate as compared with other prior art shielding techniques.Type: GrantFiled: July 21, 2009Date of Patent: September 20, 2011Assignee: International Business Machines CorporationInventors: Phillip Francis Chapman, David Goren, Rajendran Krishnasamy, Benny Sheinman, Shlomo Shlafman, Raminderpal Singh, Wayne H. Woods
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Publication number: 20110018094Abstract: A novel and useful apparatus for and method of providing noise isolation between integrated circuit devices on a semiconductor chip. The invention addresses the problem of noise generated by digital switching devices in an integrated circuit chip that may couple through the silicon substrate into sensitive analog circuits (e.g., PLLs, transceivers, ADCs, etc.) causing a significant degradation in performance of the sensitive analog circuits. The invention utilizes a deep trench capacitor (DTCAP) device connected to ground to isolate victim circuits from aggressor noise sources on the same integrated circuit chip.Type: ApplicationFiled: July 21, 2009Publication date: January 27, 2011Applicant: International Business Machines CorporationInventors: Phillip Francis Chapman, David Goren, Rajendran Krishnasamy, Benny Sheinman, Shlomo Shlafman, Raminderpal Singh, Wayne H. Woods
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Publication number: 20100249976Abstract: A method and system for evaluating a performance of a semiconductor manufacturing tool while manufacturing microelectronic devices are disclosed. At least one report is generated based on executions of at least one statistical test. The report includes at least one heat map having rows that correspond to sensors, columns that correspond to trace data obtained during recipe steps, and cells at the intersection of the rows and the columns. At least one sensor in the tool obtains trace data of a recipe step while manufacturing at least one microelectronic device. A computing device analyzes the obtained trace data to determine a level of operational significance found in the data and assigns a score to the trace data that indicates a level of operational significance. Then, the computing device places the score in a corresponding cell of the heat map. A user uses the cell for evaluating the tool performance.Type: ApplicationFiled: March 31, 2009Publication date: September 30, 2010Applicant: International Business Machines CorporationInventors: Ehud Aharoni, Robert J. Baseman, Ramona Kei, Oded Margalit, Kevin Mackey, Michal Rosen-Zvi, Raminderpal Singh, Noam Slonim, Hong Lin, Fateh All Tipu, Adam Daniel Ticknor, Timothy M. McCormack
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Publication number: 20090031260Abstract: A method, computer program and system for the optimization of semiconductor process parameters given a pre-specified set of targets and constraints on electrical performance metrics are disclosed. Semiconductor process engineers who are not expert in the art of electrical analysis or mathematical optimization can readily use the method of this invention in optimizing semiconductor process parameters. Accommodates the differences in design styles, metal layer routing, and electrical metrics using priority schedules that are easy to input and understand. Enables the exploration of the process parameter space using primitive process tolerances and accurate electrical information provided by field solvers and circuit analysis programs.Type: ApplicationFiled: July 25, 2007Publication date: January 29, 2009Inventors: Matthew Angyal, Alina Deutsch, Ibrahim M. Elfadel, Raminderpal Singh, Theodorus E. Standaert, Wayne H. Woods
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Patent number: 7309898Abstract: A method and apparatus for improving the latchup tolerance of circuits embedded in an integrated circuit while avoiding the introduction of noise from such tolerance into the power rails.Type: GrantFiled: May 20, 2002Date of Patent: December 18, 2007Assignee: International Business Machines CorporationInventors: Raminderpal Singh, Steven Howard Voldman
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Patent number: 7246055Abstract: An open system for multiple discrete, geographically disperse simulation engines to communicate with each other across a distributed electronic network, such as the Internet, comprises a portal accessible to the simulation engines over the network. Local portions of the simulation may be run separately by each simulation engine, and the output data files are stored on and managed by the portal. A co-simulating engine may request an output data file stored by the portal and use that data as input for its downstream portion of the simulation. In this fashion, multiple geographically disperse simulation engines can test bench their designs in an open, network centric simulation environment.Type: GrantFiled: August 28, 2000Date of Patent: July 17, 2007Assignee: Cadence Design Systems, Inc.Inventor: Raminderpal Singh
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Patent number: 7139990Abstract: A sub-circuit based extraction method which extracts a multi-finger MOS transistor directly as a sub-circuit is described. By adding three marking layers, the method provides the layout extracted netlist with a complete list of device geometric parameters corresponding to the device properties as presented in the sub-circuit model based schematic netlist. By performing a layout-versus-schematic comparison based on all geometric parameters extracted, the layout checking is performed in a complete and accurate way where each device parameter is checked against the corresponding design schematic. This complete and accurate geometric parameter comparison enhances the confidence level of the layout physical verification.Type: GrantFiled: March 23, 2004Date of Patent: November 21, 2006Assignee: International Business Machines CorporationInventors: Raminderpal Singh, Yue Tan, Jean-Oliver Plouchart, Lawrence F. Wagner, Jr., Mohamed Talbi, John M. Safran, Kun Wu
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Patent number: 7089512Abstract: A method of analyzing and designing circuits comprising creating a set of interpolated models for transistor devices; creating a set of characterized (direct fit) models for the transistor devices; analyzing the transistor devices within a netlist for matches in the set of characterized models; and providing a choice of using the matched characterized models or one of the interpolated models in designing the circuits.Type: GrantFiled: March 15, 2004Date of Patent: August 8, 2006Assignee: International Business Machines CorporationInventors: Joseph A. Iadanza, Raminderpal Singh
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Patent number: 7020857Abstract: A method and apparatus for analyzing an integrated circuit design for pnpn structures which are likely to latchup or cause injection of noise into the substrate. Once qualifying pnpn structures are identified, the method and apparatus automatically inserts a noise and latchup suppression circuit of the designers' choice into the pnpn structure to eliminate the latchup and/or noise concerns.Type: GrantFiled: May 20, 2002Date of Patent: March 28, 2006Assignee: International Business Machines CorporationInventors: Raminderpal Singh, Steven Howard Voldman
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Patent number: 7000214Abstract: A method for designing an integrated circuit having multiple voltage domains, including: (a) generating a logical integrated circuit design from information contained in a high-level design file, the high-level design file defining global connection declarations and voltage domain connection declarations; (b) synthesizing the logical integrated circuit design into a synthesized integrated circuit design based upon the logical integrated circuit design, information in a preferred components file and information in a voltage domain definition file; (c) generating a noise model from the synthesized integrated circuit design based on information in the voltage domain definition file and a design constraint file; and (d) simulating the noise model against constraints in the design constraint file and constraints in a circuit level profile file to determine if the synthesized integrated circuit design meets predetermined noise simulation targets.Type: GrantFiled: November 19, 2003Date of Patent: February 14, 2006Assignee: International Business Machines CorporationInventors: Joseph A. Iadanza, Raminderpal Singh, Sebastian T. Ventrone, Ivan L. Wemple
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Patent number: 6954920Abstract: A method, program product, and design tool for automatic transmission line selection in application specific integrated circuits. The method includes: determining route paths between blocks of an application specific integrated circuit; scanning the route paths for transmission line replacement candidates; and, for each transmission line replacement candidate, automatically selecting a buffered wire or a transmission line to implement the route path.Type: GrantFiled: June 30, 2003Date of Patent: October 11, 2005Assignee: International Business Machines CorporationInventors: Peter J. Jenkins, Raminderpal Singh, Sebastian T. Ventrone
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Publication number: 20050216873Abstract: A sub-circuit based extraction method which extracts a multi-finger MOS transistor directly as a sub-circuit is described. By adding three marking layers, the method provides the layout extracted netlist with a complete list of device geometric parameters corresponding to the device properties as presented in the sub-circuit model based schematic netlist. By performing a layout-versus-schematic comparison based on all geometric parameters extracted, the layout checking is performed in a complete and accurate way where each device parameter is checked against the corresponding design schematic. This complete and accurate geometric parameter comparison enhances the confidence level of the layout physical verification.Type: ApplicationFiled: March 23, 2004Publication date: September 29, 2005Inventors: Raminderpal Singh, Yue Tan, Jean-Oliver Plouchart, Lawrence Wagner, Mohamed Talbi, John Safran, Kun Wu
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Patent number: 6950997Abstract: A method for designing an integrated circuit by a user, including: evaluating noise parameters for design elements of an integrated circuit design; determining if the noise parameters meet noise constraints of the integrated circuit design; and if the noise parameters do not meet the noise constraints, selecting alternative design elements having noise parameters that do meet the noise constraints.Type: GrantFiled: April 28, 2003Date of Patent: September 27, 2005Assignee: International Business Machines CorporationInventors: Carl E. Dickey, Scott M. Parker, Raminderpal Singh
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Publication number: 20050204318Abstract: A method of analyzing and designing circuits comprising creating a set of interpolated models for transistor devices; creating a set of characterized (direct fit) models for the transistor devices; analyzing the transistor devices within a netlist for matches in the set of characterized models; and providing a choice of using the matched characterized models or one of the interpolated models in designing the circuits.Type: ApplicationFiled: March 15, 2004Publication date: September 15, 2005Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Joseph Iadanza, Raminderpal Singh
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Publication number: 20050108667Abstract: A method for designing an integrated circuit having multiple voltage domains, including: (a) generating a logical integrated circuit design from information contained in a high-level design file, the high-level design file defining global connection declarations and voltage domain connection declarations; (b) synthesizing the logical integrated circuit design into a synthesized integrated circuit design based upon the logical integrated circuit design, information in a preferred components file and information in a voltage domain definition file; (c) generating a noise model from the synthesized integrated circuit design based on information in the voltage domain definition file and a design constraint file; and (d) simulating the noise model against constraints in the design constraint file and constraints in a circuit level profile file to determine if the synthesized integrated circuit design meets predetermined noise simulation targets.Type: ApplicationFiled: November 19, 2003Publication date: May 19, 2005Applicant: International Business Machines CorporationInventors: Joseph Iadanza, Raminderpal Singh, Sebastian Ventrone, Ivan Wemple