Abstract: A vertically stacked coplanar transmission line structure for an IC (integrated circuit) is provided which has superior loss and reflection characteristics relative to conventional on-chip transmission line designs. A simple embodiment of the vertically stacked coplanar transmission line structure comprises a micro-strip pair of first and second vertically stacked coplanar conductors, each comprising a metal layer, a next metal layer down, and an intermediate connecting via layer in between the metal layer and the next metal layer down.

Abstract: A method for designing integrated circuits comprising: partitioning interconnects of an integrated circuit design based on partition criteria to create sets of interconnect partitions; selecting at least one analysis method from a set of analysis methods to be performed on interconnects of each set of interconnect partitions; and performing each selected analysis method on interconnects of each corresponding interconnect partition.

Abstract: A method, program product, and design tool for automatic transmission line selection in application specific integrated circuits. The method includes: determining route paths between blocks of an application specific integrated circuit; scanning the route paths for transmission line replacement candidates; and, for each transmission line replacement candidate, automatically selecting a buffered wire or a transmission line to implement the route path.

Abstract: An integrated circuit having either or both ESD and noise suppression devices that use the inherent resistance in the substrate as an ESD trigger and/or part of the noise suppression.

Abstract: A structure and associated method to determine an actual resistance value of a calibration resistor within a semiconductor device. The semiconductor device comprises a capacitor, a calibration resistor, and a calibration circuit. A voltage applied to the calibration resistor produces a current flow through the calibration resistor to charge the capacitor. The calibration circuit is adapted to measure an actual time required to charge the capacitor. The calibration circuit is further adapted calculate an actual resistance value of the calibration resistor based on the actual time required to charge the capacitor and a capacitance value of the capacitor.

Abstract: A method for designing an integrated circuit by a user, including: evaluating noise parameters for design elements of an integrated circuit design; determining if the noise parameters meet noise constraints of the integrated circuit design; and if the noise parameters do not meet the noise constraints, selecting alternative design elements having noise parameters that do meet the noise constraints.

Abstract: A method for designing integrated circuits comprising: partitioning interconnects of an integrated circuit design based on partition criteria to create sets of interconnect partitions; selecting at least one analysis method from a set of analysis methods to be performed on interconnects of each set of interconnect partitions; and performing each selected analysis method on interconnects of each corresponding interconnect partition.

Abstract: An integrated circuit having structure for isolating circuit sections having at least one differing characteristic. The structure includes a chip guard ring for each circuit section having the at least one differing characteristic. Providing multiple chip guard rings allows for isolation of circuit sections and prevention of ionic contamination, but without increased expense and size. In addition, it is practicable with any IC. The invention also may include an interconnect for electrical connectivity about a chip guard ring.

Abstract: An integrated circuit having structure for isolating circuit sections having at least one differing characteristic. The structure includes a chip guard ring for each circuit section having the at least one differing characteristic. Providing multiple chip guard rings allows for isolation of circuit sections and prevention of ionic contamination, but without increased expense and size. In addition, it is practicable with any IC. The invention also may include an interconnect for electrical connectivity about a chip guard ring.

Abstract: A method and apparatus for identifying parasitic pnpn structures in an integrated circuit, and automatically inserting a noise latchup suppression circuit in such identified pnpn structure.

Abstract: An integrated circuit having either or both ESD and noise suppression devices that use the inherent resistance in the substrate as an ESD trigger and/or part of the noise suppression.