Abstract: In one embodiment, the present invention includes a method for receiving at a transceiver from a baseband processor digital control information that includes both event and schedule information, storing the digital control information in a storage of the transceiver, and operating the transceiver according to the event and schedule information.

Abstract: A bandpass delta sigma truncator that truncates multi-bit digital input signals to digital output signals (24) having a selected number of the most significant data bits of the digital input signals and a method of truncating multi-bit digital signals. The remaining least significant data bits (3) of the input signals are (a) time delayed (26) by a period of time equal to the time between successive input signals and multiplied by a number (30) related to the ratio of a selected frequency to the frequency of the input signals and the results of the multiplication are added (32) to signs extensions (11) of the input signals, and (b) time delayed by a period of time equal to twice the time between successive input signals and after inversion (28) are added (32) to the sign extensions of the input signals.

Abstract: An RF transmitter (104) includes a shared local oscillator circuit (126), transmit path circuitry (120, 122, 124), a divider (134), and a lowpass filter (322). The shared local oscillator circuit (126) generates a shared LO signal (116). The transmit path circuitry (120, 122, 124) mixes a baseband signal (107) and an IF mixing signal (116) to provide an IF signal (112), and converts the IF signal (112) to an RF transmit signal (105) at a desired frequency using an RF mixing signal received at a mixing input thereof. The divider (134) divides the shared LO signal (116) to provide an unfiltered RF mixing signal. The lowpass filter (322) has an input for receiving the unfiltered RF mixing signal, and an output coupled to the mixing input of the transmit path circuitry (120, 122, 124) for providing the RF mixing signal.

Abstract: A digital to analog converter which produces a non-return to zero output voltage. Two SIN DAC converters having return to zero (RZ) output voltages connected to provide a common NRZ output signal. The SIN DAC converters receive the digital signal and a delayed version of the digital signal. The reference sine voltage applied to each SIN DAC have a respective phase shift so that the outputs from each SIN DAC are phase shifted. The combined phase shifted output signals produce an NRZ signal with a reduced susceptibility to clock signal jitter, and which contain significantly less high frequency content than the RZ output signal from a SIN DAC.

Abstract: A continuous time delta-sigma analog to digital converter is disclosed. A summing junction receives an input analog signal to be digitized and a feedback signal. A loop filter receives the combined signals from the summing junction, and a course analog to digital converter converts the combined signal to a multi-bit digital number. A sin DAC provides a feedback signal to the summing junction, by reconverting the multi-bit digital signal to an analog signal. The sin DAC produces a linear output signal having a reduced phase jitter, resulting in a lower noise floor for the multi-digital signal. The sin DAC may be an NRZ sin DAC which avoids stringent linearity requirements on the summing junction.

Abstract: A digital to analog converter which produces a non-return to zero output voltage. Two SIN DAC converters having return to zero (RZ) output voltages connected to provide a common NRZ output signal. The SIN DAC converters receive the digital signal and a delayed version of the digital signal. The reference sine voltage applied to each SIN DAC have a respective phase shift so that the outputs from each SIN DAC are phase shifted. The combined phase shifted output signals produce an NRZ signal with a reduced susceptibility to clock signal jitter, and which contain significantly less high frequency content than the RZ output signal from a SIN DAC.

Abstract: A continuous time delta-sigma analog to digital converter is disclosed. A summing junction receives an input analog signal to be digitized and a feedback signal. A loop filter receives the combined signals from the summing junction, and a course analog to digital converter converts the combined signal to a multi-bit digital number. A sin DAC provides a feedback signal to the summing junction, by reconverting the multi-bit digital signal to an analog signal. The sin DAC produces a linear output signal having a reduced phase jitter, resulting in a lower noise floor for the multi-digital signal. The sin DAC may be an NRZ sin DAC which avoids stringent linearity requirements on the summing junction.

Abstract: A transconductor block including a Czarnul tuning network, transconductance resistors, an input voltage follower amplifier, a common mode circuit, PMOS transistors coupled in cascode configuration, an input current source, and high gain amplifiers that drive NMOS transistors at the output. The input voltage follower amplifier receives a differential input signal including a common mode voltage and applies the differential input signal to the Czarnul tuning network. The Czarnul tuning network includes series resistors and is coupled in parallel with the transconductance resistors. The common mode circuit receives the differential input signal and a reference common mode voltage and provides a bias voltage and a common mode feedback voltage. The common mode circuit asserts the common mode feedback voltage to the output PMOS transistors to establish a DC output current and to minimize drift of the common mode voltage of the transconductance block.

Abstract: A circuit and method for initiating operation of a bandgap reference circuit. A start pulse circuit provides a start pulse when the bandgap circuit is powered up. A transistor receives the pulse as an input, and applies the pulse to a regenerative bandgap reference circuit. The bandgap reference circuit output voltage is forced above a normal output voltage, producing a feedback current through the bandgap reference circuit, providing a current level which exceeds the normal stable operating level and output voltage level range. When the pulse ceases, the regenerative bandgap reference circuit output voltage decreases to its normal stable value, and the regenerative bandgap reference circuit is placed in its normal stable operating state.