Patents by Inventor Ramnath Venkatraman

Ramnath Venkatraman has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9158319
    Abstract: In one embodiment, an integrated circuit (IC) device includes a first logic block having performance characteristics, a first critical path monitor (CPM) configured to monitor the performance characteristics of the first logic block, and a first CPM envelope circuit enveloping the first CPM. The first logic block is configured to operate in at least one of a first functional mode and a first scan mode. The first CPM is adapted to operate in at least one of a second functional mode and a second scan mode. The first and second functional modes use higher clock frequencies, respectively, than the first and second scan modes. The first CPM envelope circuit comprises a clock-gate circuit adapted to allow the IC device to operate in a mixed mode, wherein the first CPM operates in the second functional mode while the first logic block operates in the first scan mode.
    Type: Grant
    Filed: November 25, 2013
    Date of Patent: October 13, 2015
    Assignee: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
    Inventors: Manjunatha Gowda, Ramnath Venkatraman, Thai M. Nguyen, Hai H. Tan, Prasad Subbarao
  • Publication number: 20150109052
    Abstract: In one embodiment, an integrated circuit (IC) device includes a first logic block having performance characteristics, a first critical path monitor (CPM) configured to monitor the performance characteristics of the first logic block, and a first CPM envelope circuit enveloping the first CPM. The first logic block is configured to operate in at least one of a first functional mode and a first scan mode. The first CPM is adapted to operate in at least one of a second functional mode and a second scan mode. The first and second functional modes use higher clock frequencies, respectively, than the first and second scan modes. The first CPM envelope circuit comprises a clock-gate circuit adapted to allow the IC device to operate in a mixed mode, wherein the first CPM operates in the second functional mode while the first logic block operates in the first scan mode.
    Type: Application
    Filed: November 25, 2013
    Publication date: April 23, 2015
    Applicant: LSI Corporation
    Inventors: Manjunatha Gowda, Ramnath Venkatraman, Thai M. Nguyen, Hai H. Tan, Prasad Subbarao
  • Patent number: 8738940
    Abstract: A rush-in current controller includes a clock module connected to provide a delayed sleep control signal based on counting a preset number of clock cycles corresponding to an input sleep control signal. Additionally, the rush-in current controller includes a ring oscillator module connected to maintain the delayed sleep control signal based on counting a preset number of ring oscillator cycles corresponding to a virtual power supply line voltage. A method of controlling a rush-in current includes providing a delayed sleep control signal based on counting a preset number of clock cycles corresponding to an input sleep control signal and maintaining the delayed sleep control signal based on counting a preset number of ring oscillator cycles corresponding to a virtual power supply line voltage.
    Type: Grant
    Filed: September 6, 2011
    Date of Patent: May 27, 2014
    Assignee: LSI Corporation
    Inventors: Ramnath Venkatraman, Shashidhara S. Bapat, Ruggero Castagnetti
  • Publication number: 20140040842
    Abstract: A method of reducing total power dissipation for logic cells using Boolean equations includes selecting a path, identifying at least one group of logic cells for analysis in the path, and deriving Boolean equations for the at least one group of logic cells. Additionally, the method includes listing possible logic cell implementations for each Boolean equation while maintaining original transistor values, verifying path timing for the possible logic cell implementations to provide retained logic cells that achieve a path timing requirement, computing a total power dissipation for the retained logic cells, and choosing a logic cell set from the retained logic cells corresponding to a minimum total power dissipation for the path. A method for reducing total power dissipation for logic cell sets and a processor configured to reduce total power dissipation for groups of logic cells are also provided.
    Type: Application
    Filed: October 14, 2013
    Publication date: February 6, 2014
    Applicant: LSI Corporation
    Inventors: Benjamin Mbouombouo, Ramnath Venkatraman, Ruggero Castagnetti
  • Publication number: 20140028364
    Abstract: A critical path monitor (CPM), a method of setting supply voltage based on output of a CPM and an integrated circuit (IC) incorporating the CPM. In one embodiment, the CPM includes: (1) an edge detector configured to produce a thermometer output over a plurality of clock cycles and (2) a min_max recorder, coupled to the edge detector and configured to record minimum and maximum values of the thermometer output during a polling interval.
    Type: Application
    Filed: July 27, 2012
    Publication date: January 30, 2014
    Applicant: LSI Corporation
    Inventors: Ramnath Venkatraman, Prasad Subbarao, Ruggero Castagnetti
  • Patent number: 8624352
    Abstract: An IC capacitor bank includes a plurality of high-k metal-insulator-metal (MIM) capacitors connected to a pair of conductive traces. A fusible trace located on an end of one of the pair of conductive traces forms a capacitor column connected between supply lines, such that failure of a dielectric in the MIM capacitors causes the fusible trace to at least partially open thereby limiting a fault current in the capacitor column. Additionally, a method of manufacturing an IC capacitor bank includes providing a plurality of high-k metal-insulator-metal (MIM) capacitors connected to a pair of conductive traces and locating a fusible trace on an end of the pair of conductive traces to form a capacitor column that is connected between supply lines, such that failure of a dielectric in the MIM capacitors causes the fusible trace to at least partially open thereby limiting a fault current in the capacitor column.
    Type: Grant
    Filed: November 24, 2010
    Date of Patent: January 7, 2014
    Assignee: LSI Corporation
    Inventors: Bonnie E. Weir, Edward B. Harris, Ramnath Venkatraman
  • Patent number: 8589853
    Abstract: A method of reducing total power dissipation for logic cells includes selecting a distribution of logic cells corresponding to at least one path, computing a dynamic to static power ratio for each logic cell in the distribution of logic cells and ranking the dynamic to static power ratio for each logic cell into a lower group, a middle group and an upper group of logic cells. Additionally, the method includes swapping the lower group of logic cells and the upper group of logic cells for a reconfigured middle group of logic cells and verifying path timing for the reconfigured middle group of logic cells. Methods of reducing total power dissipation using Boolean equations and for logic cell sets are also provided.
    Type: Grant
    Filed: May 9, 2011
    Date of Patent: November 19, 2013
    Assignee: LSI Corporation
    Inventors: Benjamin Mbouombouo, Ramnath Venkatraman, Ruggero Castagnetti
  • Publication number: 20130166930
    Abstract: Described embodiments provide for a memory system adapted to enable power-gating in one or more memories. Each memory has a corresponding timing characteristic. A monitor in the memory system determines a timing threshold and determines whether the timing characteristic of a memory is at least equal to the timing threshold. If the corresponding timing characteristic is at least equal to the timing threshold, power-gating is applied to the memory.
    Type: Application
    Filed: December 23, 2011
    Publication date: June 27, 2013
    Inventors: Ting Zhou, Ruggero Castagnetti, Ramnath Venkatraman
  • Publication number: 20130166931
    Abstract: Described embodiments provide for a memory system which power-gates a memory operating at a first clock. Control logic in the memory system activates, during a rising edge of a second clock, the memory from a sleep mode. The memory is accessed. After a cycle of the first clock, the control logic asserts a power-gating signal, thereby returning the memory to the sleep mode. The frequency of the second clock is less than a frequency of the first clock.
    Type: Application
    Filed: December 23, 2011
    Publication date: June 27, 2013
    Inventors: Ruggero Castagnetti, Ting Zhou, Ramnath Venkatraman
  • Publication number: 20130154109
    Abstract: The disclosure provides an interposer with conductive paths, a three-dimensional integrated circuit (3D IC), a method of reducing capacitance associated with conductive paths in an interposer and a method of manufacturing an interposer. In one embodiment the interposer includes: (1) a semiconductor substrate that is doped with a dopant, (2) conductive paths located within said semiconductor substrate and configured to provide electrical routes therethrough and (3) an ohmic contact region located within said semiconductor substrate and configured to receive a back bias voltage.
    Type: Application
    Filed: December 16, 2011
    Publication date: June 20, 2013
    Applicant: LSI Corporation
    Inventors: Ramnath Venkatraman, John W. Osenbach, Anwar Ali, Donald E. Hawk, Robert J. Madge
  • Patent number: 8429586
    Abstract: A basic cell circuit architecture having plurality of cells with fixed transistors configurable for the formation of logic devices and single and dual port memory devices within a structured ASIC is provided. Different configurations of ensuing integrated circuits are achieved by forming variable interconnect layers above the fixed structures. The circuit architecture can achieve interconnection of transistors within a single cell or across multiple cells. The interconnection can be configured to form basic logic gates as well as more complex digital and analog subsystems. In addition, each cell contains a layout of transistors that can be variably coupled to achieve a memory device, such as a SRAM device. By having the capability of forming a logic circuit element, a memory device, or both, the circuit architecture is both memory-centric and logic-centric, and more fully adaptable to modern-day SoCs.
    Type: Grant
    Filed: March 20, 2012
    Date of Patent: April 23, 2013
    Assignee: LSI Corporation
    Inventors: Ramnath Venkatraman, Michael N. Dillon, David A. Gardner, Carl A. Monzel, III, Subramanian Ramesh, Robert C. Armstrong, Gary S. Delp, Scott A. Peterson
  • Patent number: 8411399
    Abstract: An integrated circuit power supply decoupling circuit includes a capacitor and a protection circuit. The capacitor has a first terminal and a second terminal. The protection circuit includes a first transistor having a first conduction path, and a second transistor having a second conduction path. One terminal of the first conduction path is connected to the first terminal of the capacitor, and another terminal of the first conduction path is connected to a first power supply rail. One terminal of the second conduction path is connected to the second terminal of the capacitor, and another terminal of the second conduction path is connected to a second power supply rail.
    Type: Grant
    Filed: July 19, 2010
    Date of Patent: April 2, 2013
    Assignee: LSI Corporation
    Inventors: Ramnath Venkatraman, Ruggero Castagnetti
  • Publication number: 20130057338
    Abstract: A rush-in current controller includes a clock module connected to provide a delayed sleep control signal based on counting a preset number of clock cycles corresponding to an input sleep control signal. Additionally, the rush-in current controller includes a ring oscillator module connected to maintain the delayed sleep control signal based on counting a preset number of ring oscillator cycles corresponding to a virtual power supply line voltage. A method of controlling a rush-in current includes providing a delayed sleep control signal based on counting a preset number of clock cycles corresponding to an input sleep control signal and maintaining the delayed sleep control signal based on counting a preset number of ring oscillator cycles corresponding to a virtual power supply line voltage.
    Type: Application
    Filed: September 6, 2011
    Publication date: March 7, 2013
    Applicant: LSI Corporation
    Inventors: Ramnath Venkatraman, Shashidhara S. Bapat, Ruggero Castagnetti
  • Publication number: 20120290994
    Abstract: A method of reducing total power dissipation for logic cells includes selecting a distribution of logic cells corresponding to at least one path, computing a dynamic to static power ratio for each logic cell in the distribution of logic cells and ranking the dynamic to static power ratio for each logic cell into a lower group, a middle group and an upper group of logic cells. Additionally, the method includes swapping the lower group of logic cells and the upper group of logic cells for a reconfigured middle group of logic cells and verifying path timing for the reconfigured middle group of logic cells. Methods of reducing total power dissipation using Boolean equations and for logic cell sets are also provided.
    Type: Application
    Filed: May 9, 2011
    Publication date: November 15, 2012
    Applicant: LSI Corporation
    Inventors: Benjamin Mbouombouo, Ramnath Venkatraman, Ruggero Castagnetti
  • Publication number: 20120175683
    Abstract: A basic cell circuit architecture having plurality of cells with fixed transistors configurable for the formation of logic devices and single and dual port memory devices within a structured ASIC is provided. Different configurations of ensuing integrated circuits are achieved by forming variable interconnect layers above the fixed structures. The circuit architecture can achieve interconnection of transistors within a single cell or across multiple cells. The interconnection can be configured to form basic logic gates as well as more complex digital and analog subsystems. In addition, each cell contains a layout of transistors that can be variably coupled to achieve a memory device, such as a SRAM device. By having the capability of forming a logic circuit element, a memory device, or both, the circuit architecture is both memory-centric and logic-centric, and more fully adaptable to modern-day SoCs.
    Type: Application
    Filed: March 20, 2012
    Publication date: July 12, 2012
    Applicant: LSI Corporation
    Inventors: Ramnath Venkatraman, Michael N. Dillon, David A. Gardner, Carl Anthony Monzel, III, Subramanian Ramesh, Robert C. Armstrong, Gary Scott Delp, Scott Allen Peterson
  • Publication number: 20120126364
    Abstract: An IC capacitor bank includes a plurality of high-k metal-insulator-metal (MIM) capacitors connected to a pair of conductive traces. A fusible trace located on an end of one of the pair of conductive traces forms a capacitor column connected between supply lines, such that failure of a dielectric in the MIM capacitors causes the fusible trace to at least partially open thereby limiting a fault current in the capacitor column. Additionally, a method of manufacturing an IC capacitor bank includes providing a plurality of high-k metal-insulator-metal (MIM) capacitors connected to a pair of conductive traces and locating a fusible trace on an end of the pair of conductive traces to form a capacitor column that is connected between supply lines, such that failure of a dielectric in the MIM capacitors causes the fusible trace to at least partially open thereby limiting a fault current in the capacitor column.
    Type: Application
    Filed: November 24, 2010
    Publication date: May 24, 2012
    Applicant: LSI Corporation
    Inventors: Bonnie E. Weir, Edward B. Harris, Ramnath Venkatraman
  • Patent number: 8178909
    Abstract: An improved integrated circuit cell architecture is provided for configurability between a memory cell or logic elements. The cell architecture is configured on variable layers above a first layer of metal, with the first layer of metal and layers therebelow reserved as fixed layers. By coupling a maximum of two layout cells together, a single-port or dual-port memory cell is realized. Likewise, by interconnecting transistors within a single cell or transistors among two or more cells, a logic device is realized. Within each cell, the bit lines are arranged on a layer separate from the wordlines, and extend orthogonal to each other.
    Type: Grant
    Filed: September 23, 2011
    Date of Patent: May 15, 2012
    Assignee: LSI Corporation
    Inventors: Ramnath Venkatraman, Carl Anthony Monzel, III, Subramanian Ramesh
  • Patent number: 8166440
    Abstract: A basic cell circuit architecture having plurality of cells with fixed transistors configurable for the formation of logic devices and/or single/dual port memory devices within a structured ASIC is provided. Different configurations of ensuing integrated circuits are achieved by forming variable interconnect layers above the fixed structures. The circuit architecture can achieve interconnection of transistors within a single cell and/or across multiple cells. The interconnection can be configured to form basic logic gates as well as more complex digital and analog subsystems. In addition, each cell contains a layout of transistors that can be variably coupled to achieve a memory device, such as a SRAM device. By having the capability of forming either a logic circuit element, a memory device, or both, the circuit architecture is both memory-centric and logic-centric, and more fully adaptable to modern-day SoCs.
    Type: Grant
    Filed: June 16, 2008
    Date of Patent: April 24, 2012
    Assignee: LSI Corporation
    Inventors: Ramnath Venkatraman, Michael N. Dillon, David A. Gardner, Carl Anthony Monzel, III, Subramanian Ramesh, Robert C. Armstrong, Gary Scott Delp, Scott Allen Peterson
  • Patent number: 8112734
    Abstract: A method incorporating adaptive body biasing into an integrated circuit design flow includes the steps of (A) adding adaptive body biasing input/outputs (I/Os) during a bonding layout stage of the integrated circuit design flow, (B) floorplanning the integrated circuit design, (C) generating an adaptive body biasing mesh and (D) generating a layout of the integrated circuit design based upon a plurality of adaptive body biasing corners.
    Type: Grant
    Filed: September 29, 2008
    Date of Patent: February 7, 2012
    Assignee: LSI Corporation
    Inventors: Benjamin Mbouombouo, Ramnath Venkatraman, Ruggero Castagnetti
  • Publication number: 20120012896
    Abstract: An improved integrated circuit cell architecture is provided for configurability between a memory cell or logic elements. The cell architecture is configured on variable layers above a first layer of metal, with the first layer of metal and layers therebelow reserved as fixed layers. By coupling a maximum of two layout cells together, a single-port or dual-port memory cell is realized. Likewise, by interconnecting transistors within a single cell or transistors among two or more cells, a logic device is realized. Within each cell, the bit lines are arranged on a layer separate from the wordlines, and extend orthogonal to each other.
    Type: Application
    Filed: September 23, 2011
    Publication date: January 19, 2012
    Inventors: Ramnath Venkatraman, Carl Anthony Monzel, III, Subramanian Ramesh