Abstract: A hybrid computer that comprises a sequential processor, a single instruction massively parallel (SIMD) processor, and shared memory module that is shared between the sequential processor and the SIMD processor.

Abstract: NAND-based content addressable memory is provided with a memory cell including two programmable resistive elements, such as memristors. These memory cells can be used to provide a programmable resistive address decoder. Such decoders can improve computer hardware performance in various ways: 1) improved translation lookaside buffers, 2) improved cache memory, and 3) by eliminating physical addresses entirely.

Abstract: NAND-based content addressable memory is provided with a memory cell including two programmable resistive elements, such as memristors. These memory cells can be used to provide a programmable resistive address decoder. Such decoders can improve computer hardware performance in various ways: 1) improved translation lookaside buffers, 2) improved cache memory, and 3) by eliminating physical addresses entirely.

Abstract: Memory circuitry comprises memory cells having two terminals and a feedback path connected between the two terminals. The feedback path is used to adaptively amplify identical programming pulses that serve to change memory states of the memory cell, and the amplification is based on a current resistive level of the memory cell, which may for example be a multi-level memory cell.

Abstract: A computerized method of creating a circuit logic model of a VLSI device, comprising mapping a plurality of logic function patterns of one or more circuits of a VLSI device through a plurality of probe iterations and generating a circuit logic model of the circuit(s) by reconstructing a logical function of a combinatorial logic of the circuit(s) based on analysis of the logic function patterns. Each of the probe iteration comprises switching between scan shift mode and functional mode of the VLSI device such that while the VLSI device operates in scan shift mode register(s) associated with the circuit(s) is accessed and while the VLSI device operates in functional mode external pin(s) of the VLSI device associated with the circuit(s) is probed and mapping a respective one of the logic function patterns according to a logic state of one or more bits in the register(s) and/or the external pin(s).

Abstract: Memory circuitry comprises memory cells having two terminals and a feedback path connected between the two terminals. The feedback path is used to adaptively amplify identical programming pulses that serve to change memory states of the memory cell, and the amplification is based on a current resistive level of the memory cell, which may for example be a multi-level memory cell.

Abstract: A computerized method of creating a circuit logic model of a VLSI device, comprising mapping a plurality of logic function patterns of one or more circuits of a VLSI device through a plurality of probe iterations and generating a circuit logic model of the circuit(s) by reconstructing a logical function of a combinatorial logic of the circuit(s) based on analysis of the logic function patterns. Each of the probe iteration comprises switching between scan shift mode and functional mode of the VLSI device such that while the VLSI device operates in scan shift mode register(s) associated with the circuit(s) is accessed and while the VLSI device operates in functional mode external pin(s) of the VLSI device associated with the circuit(s) is probed and mapping a respective one of the logic function patterns according to a logic state of one or more bits in the register(s) and/or the external pin(s).

Abstract: A neuronal recording system featuring a large number of electrodes and a portable wireless front-end integrated circuit for signal processing for low-power spike detection and alignment. The system is configured as a Neuroprocessor and introduces hardware architectures for automatic spike detection and alignment algorithms. The Neuroprocessor can be placed next to the recording electrodes and provide for all stages of spike processing, stimulating neuronal tissues and wireless communications to a host computer. Some of the algorithms are based on principal component analysis (PCA). Others employ a novel Integral Transform. The algorithms execute autonomously, but require off-line training and setting of computational parameters. Pre-recorded neuronal signals evaluate the accuracy of the proposed algorithms and architectures: The recorded data are processed by a standard PCA spike sorting software algorithm, as well as by the several hardware algorithms, and the outcomes are compared.

Abstract: A hybrid computer that comprises a sequential processor, a single instruction massively parallel (SIMD) processor, and shared memory module that is shared between the sequential processor and the SIMD processor.

Abstract: A method for modifying a logic circuit layout to optimize circuit propagation delays for improved circuit operation is presented. The layout includes multiple logic gates connected by conductive segments. An initial layout of a physical electronic logic circuit having the plurality of logic gates is input. A respective size is determined for each of the logic gates in accordance with the initial layout and a circuit propagation delay criterion. The circuit propagation delay criterion is a joint function of properties of at least some of the logic gates and at least some of the conductive segments. A modified logic circuit layout is output. The modified logic circuit layout includes a layout of the logic gates arranged in accordance with the initial layout, where each of the logic gates is modified according to the respective determined size, thereby to obtain a modification of the logic circuit layout incorporating an optimized circuit propagation delay.

Abstract: A CMOS integrated circuit for multi-channel neuronal recording with twelve true-differential channels, band separation and digital offset calibration. The recorded signal is separated into 2 bands: a low-frequency, local field potential (LFP); and high-frequency spike data. Digitally programmable gains for the LFP and spike bands are provided. A mixed-signal front-end processor for multi-channel neuronal recording is also described. It receives twelve differential-input channels of implanted recording electrodes. A programmable cutoff HPF blocks DC and low frequency input drift at about 1 Hz. The signals are band-split at about 200 Hz to low-frequency local field potential (LFP) and high-frequency spike data (SPK), which is band limited by a programmable-cutoff LPF. The analog signals are converted into digital form, and streamed out over a serial digital bus at up to 8 Mbps.

Abstract: A universal synchronizer for preventing signals from first clock domain from causing metastability in sampling registers operating in a second clock domain. A first synchronization flip-flop receives a primary signal from the first clock domain and a second synchronization flip-flop generates a secondary signal synchronized with the second clock domain. Notably, logic is applied to intermediate signals passed between the first synchronization flip-flop and the second synchronization flip-flop.

Abstract: An inverted ladder circuit for a Digital to Analog Converter (DAC) having an input binary word representing an input value and an output current corresponding to a converted analog value. The inverted ladder circuit includes at least two fine resistor ladders, including at least an upper fine resistor ladder and a lower fine resistor ladder. The inverted ladder circuit also includes a coarse resistor ladder having a corresponding plurality of coarse ladder resistors, wherein the coarse resistor ladder slides upon the at least two fine resistor ladders. The inverted ladder circuit also includes a plurality of upper fine switches and a plurality of lower fine switches, wherein the switches operate in parallel according to the lower five bits of the input binary word. The plurality of fine ladder resistors are matched with the plurality of coarse ladder resistors to obtain current proportional to the input binary word. The output resistance and parasitic capacitance are reduced.

Abstract: A method for modifying a logic circuit layout to optimize circuit propagation delays for improved circuit operation is presented. The layout includes multiple logic gates connected by conductive segments. An initial layout of a physical electronic logic circuit having the plurality of logic gates is input. A respective size is determined for each of the logic gates in accordance with the initial layout and a circuit propagation delay criterion. The circuit propagation delay criterion is a joint function of properties of at least some of the logic gates and at least some of the conductive segments. A modified logic circuit layout is output. The modified logic circuit layout includes a layout of the logic gates arranged in accordance with the initial layout, where each of the logic gates is modified according to the respective determined size, thereby to obtain a modification of the logic circuit layout incorporating an optimized circuit propagation delay.

Abstract: A neuronal recording system featuring a large number of electrodes and a portable wireless front-end integrated circuit for signal processing for low-power spike detection and alignment. The system is configured as a Neuroprocessor and introduces hardware architectures for automatic spike detection and alignment algorithms. The Neuroprocessor can be placed next to the recording electrodes and provide for all stages of spike processing, stimulating neuronal tissues and wireless communications to a host computer. Some of the algorithms are based on principal component analysis(PCA). Others employ a novel Integral Transform. The algorithms execute autonomously, but require off-line training and setting of computational parameters. Pre-recorded neuronal signals evaluate the accuracy of the proposed algorithms and architectures: The recorded data are processed by a standard PCA spike sorting software algorithm, as well as by the several hardware algorithms, and the outcomes are compared.

Abstract: A CMOS integrated circuit for multi-channel neuronal recording with twelve true-differential channels, band separation and digital offset calibration. The recorded signal is separated into 2 bands: a low-frequency, local field potential (LFP); and high-frequency spike data. Digitally programmable gains for the LFP and spike bands are provided. A mixed-signal front-end processor for multi-channel neuronal recording is also described. It receives twelve differential-input channels of implanted recording electrodes. A programmable cutoff HPF blocks DC and low frequency input drift at about 1 Hz. The signals are band-split at about 200 Hz to low-frequency local field potential (LFP) and high-frequency spike data (SPK), which is band limited by a programmable-cutoff LPF. The analog signals are converted into digital form, and streamed out over a serial digital bus at up to 8 Mbps.

Abstract: An inverted ladder circuit for a Digital to Analog Converter (DAC) having an input binary word representing an input value and an output current corresponding to a converted analog value. The inverted ladder circuit includes at least two fine resistor ladders, including at least an upper fine resistor ladder and a lower fine resistor ladder. The inverted ladder circuit also includes a coarse resistor ladder having a corresponding plurality of coarse ladder resistors, wherein the coarse resistor ladder slides upon the at least two fine resistor ladders. The inverted ladder circuit also includes a plurality of upper fine switches and a plurality of lower fine switches, wherein the switches operate in parallel according to the lower five bits of the input binary word. The plurality of fine ladder resistors are matched with the plurality of coarse ladder resistors to obtain current proportional to the input binary word. The output resistance and parasitic capacitance are reduced.

Abstract: A wireless device is provided with a first wireless transceiver and a second wireless transceiver operative in a coordinated manner and coupled to at least one controller manager. The first wireless transceiver transmits and receives signals in accordance with a first protocol to and from a first network device of a first wireless network communicatively coupled to the apparatus, and the second wireless transceiver transmits and receives signals in accordance with a second protocol to and from a second network device of a second wireless network communicatively coupled to the apparatus. The wireless device is further provided with a network manager to coordinate the transmit and receive operations of the first wireless transceiver and said the second wireless transceiver in order to enable the wireless device to communicate contemporaneously with the first and second wireless networks.

Abstract: A single, dual form computing device is provided that incorporates the functionality of a laptop computer with that of a handheld or palm-size computing device, and allows each functionality to be selectively employed. The dual form computing device operates in one of two modes. While operating in a first “instant on” mode, the dual form computing device provides functionality similar to that of a handheld device, whereby a lengthy bootstrap process and operating system load is not required. While operating in a second “non-instant on” mode, the dual form computing device operates substantially like a laptop computer. Additionally, the dual form computing device is equipped to share input and output devices independent of the operation mode it functions in.

Abstract: A single, dual form computing device is provided that incorporates the functionality of a laptop computer with that of a handheld or palm-size computing device, and allows each functionality to be selectively employed. The dual form computing device operates in one of two modes. While operating in a first “instant on” mode, the dual form computing device provides functionality similar to that of a handheld device, whereby a lengthy bootstrap process and operating system load is not required. While operating in a second “non-instant on” mode, the dual form computing device operates substantially like a laptop computer. Additionally, the dual form computing device is equipped to share input and output devices independent of the operation mode it functions in.