Abstract: A single, dual form computing device is provided that incorporates the functionality of a laptop computer with that of a handheld or palm-size computing device, and allows each functionality to be selectively employed. The dual form computing device operates in one of two modes. While operating in a first “instant on” mode, the dual form computing device provides functionality similar to that of a handheld device, whereby a lengthy bootstrap process and operating system load is not required. While operating in a second “non-instant on” mode, the dual form computing device operates substantially like a laptop computer. Additionally, the dual form computing device is equipped to share input and output devices independent of the operation mode it functions in.

Abstract: A collection of wirelessly networked devices including first devices wirelessly networked together using a first wireless protocol that is a frequency hopping protocol, and second devices wirelessly networked together using a second wireless protocol, are operated in a coordinated manner, including proactive reduction of interference between the networked devices. In one embodiment, the first devices include at least a first and a second subset operating with a first and a second frequency hopping pattern respectively. The proactive reduction effort includes synchronized operations of the first and second subsets of the first devices, and the second devices operate in a manner complementary to the synchronized operations of the first devices. In one embodiment, the collection of wirelessly networked devices includes at least one wireless device that operates in both wireless networks in accordance with both wireless protocols.

Abstract: A single, dual form computing device is provided that incorporates the functionality of a laptop computer with that of a handheld or palm-size computing device, and allows each functionality to be selectively employed. The dual form computing device operates in one of two modes. While operating in a first “instant on” mode, the dual form computing device provides functionality similar to that of a handheld device, whereby a lengthy bootstrap process and operating system load is not required. While operating in a second “non-instant on” mode, the dual form computing device operates substantially like a laptop computer. Additionally, the dual form computing device is equipped to share input and output devices independent of the operation mode it functions in.

Abstract: A wireless device is provided with a first wireless transceiver and a second wireless transceiver operative in a coordinated manner and coupled to at least one controller manager. The first wireless transceiver transmits and receives signals in accordance with a first protocol to and from a first network device of a first wireless network communicatively coupled to the apparatus, and the second wireless transceiver transmits and receives signals in accordance with a second protocol to and from a second network device of a second wireless network communicatively coupled to the apparatus. The wireless device is further provided with a network manager to coordinate the transmit and receive operations of the first wireless transceiver and said the second wireless transceiver in order to enable the wireless device to communicate contemporaneously with the first and second wireless networks.

Abstract: A wireless device is provided with at least one wireless transceiver and at least one controller manager to transmit and receive signals wirelessly to and from network devices of a first and second wireless network, in a coordinated manner, in accordance with a first and a second protocol respectively. The wireless device is further provided with a network manager to coordinate the network devices of the first and second wireless networks to reduce interference between the network devices of the two wireless networks. In various embodiments, the reduction is effectuated through proactive avoidance of interference with dominant devices by dominated devices, whenever an interference is predicted to occur. In other embodiments, the reduction is effectuated through corresponding application of appropriate filtering to correspondingly cancel the respective interfering signals, whenever an interference is predicted to occur.

Abstract: A method system and apparatus for implementing clock delay insertion for modules of chips using programmable clock delay units are described. The system for adding a clock delay to the clock input of a module includes a module and a programmable clock delay unit pre-pended to the module and configured to add a programmed clock delay.

Abstract: A system and method of synthesizing and/or verifying a circuit from a behavioral description of that circuit. A signal ordering of signals in the circuit is defined, wherein defining a signal ordering of signals in the circuit includes specifying a relative ordering of a plurality of events within the circuit. The behavioral description is modified as a function of the signal ordering. The circuit is then synthesized and/or verified as a function of the modified behavioral description.

Abstract: Optimal parallelization of necessarily serial operations is performed by speculative parallel processing and propagation of serial marking signals to indicate valid data. An exemplary instruction marking circuit for a computer system implementing such optimization includes a series of columns, each column corresponding to one byte of a fixed length instruction line, and a length decoder in each column. Each length decoder receives a byte of the respective column, and performs a length decode independently of the other length decoders. The length decoder asserts a length signal indicative of an instruction length when the byte is the first byte of an instruction. A marking unit arrangement is coupled to the length decoders, and operates to mark each column containing a first byte of an instruction as a function of the length signals asserted by the length decoders.

Abstract: A self-timed instruction marking circuit includes a prefix handling system for processing instruction bytes having prefix bytes. Length decoders receive instruction data bytes, and perform length decoding independently of the other length decoders in the instruction marking circuit. A length decoder determines whether a byte being processed is a prefix byte to an instruction. If a length-affecting prefix byte is found, the length decoder signals a subsequent length decoder to indicate that a prefix byte has been found. The subsequent length decoder uses the prefix signal to appropriately length decode the byte being processed by the subsequent length decoder. Signals are provided to continue the self-timed marking process. Prefix handling may also be used in a multiple marking unit configuration of an instruction marking circuit.

Abstract: A self-timed instruction marking circuit includes a long instruction processing system to divide long instruction processing between two columns of the instruction marking circuit. Length decoders are interconnected across columns to signal the presence and length of long instructions. Self-timed marking can continue without alteration. The number of connections required by the instruction marking circuit are reduced. The marking process can be optimized to efficiently process all instructions by setting the definition of a long instruction such that commonly executed instructions are not included.

Abstract: An instruction execution pipeline in a computer system having variable-length instructions uses branch prediction to perform self-timed marking of instructions prior to decoding. Branch handling logic is provided in an instruction marking circuit to directly mark a target instruction of a predicted branch as the next instruction to be decoded. Additionally, a branch target FIFO may be used to store information about the location of the target instruction in the instruction stream.

Abstract: A digital neural network architecture including a forward cascade of layers of neurons, having one input channel and one output channel, for forward processing of data examples that include many data packets. Backward cascade of layers of neurons, having one input channel and one output channel, for backward propagation learning of errors of the processed data examples. Each packet being of a given size. The forward cascade is adapted to be fed, through the input channel, with a succession of data examples and to deliver a succession of partially and fully processed data examples each consisting of a plurality of packets. The fully processed data examples are delivered through the one output channel. Each one of the layers is adapted to receive as input in its input channel a first number of data packets per time unit and to deliver as output in its output channel a second number of data packets per time unit.

Abstract: Color image enhancement apparatus comprising apparatus for receiving signals representing a color image, image processing apparatus, employing the received signals, for image processing of the high spatial frequency chromatic components of a color image, and apparatus for providing a color image from the output of said image processing apparatus.

Abstract: A dynamic image representation system comprising apparatus for sensing a dynamic scene and apparatus for providing a pixel count reduced dynamic digital representation of the scene having pixel count reductions in portions of the scene not fulfilling predetermined spatial criteria and pixel count reductions in portions of the scene not undergoing change within predetermined temporal criteria.

Abstract: The apparatus is a color wide dynamic range video camera which takes a plurality of images at different exposure levels, applies neighborhood processing to each of the images, and then combines the components into a final image.

Abstract: A high flow-rate synchronizer/scheduler apparatus for a mutiprocessor system during program run-time, comprises a connection matrix for monitoring and detecting computational tasks which are allowed for execution containing a task map and a network of nodes for distributing to the processors information or computational tasks detected to be enabled by the connection matrix. The network of nodes possesses the capability of decomposing information on a pack of allocated computational tasks into messages of finer sub-packs to be sent toward the processors, as well as the capability of unifying packs of information on termination of computational tasks into a more comprehensive pack. A method of performing the synchronization/scheduling in a multiprocessor system of this apparatus is also described.

Abstract: This invention is directed to a wide dynamic range video imaging apparatus. More specifically, the invention is directed to a video imaging apparatus comprising a) a sensor for providing a plurality of video images of a scene at different exposure levels and b) a processor for processing the plurality of video images to produce a combined video image including image information from the plurality of video images by applying neighborhood transforms to the plurality of video images, the processor comprising a selector for locally selecting the operating levels of the dynamic range of the combined video image within the dynamic range of the sensor, whereby the resulting video image includes image information from the plurality of video images with enhanced information content at local areas therein.