Abstract: A driving circuit includes a driving control signal generation circuit and a multi-channel output circuit; the multi-channel output circuit includes N stage of output sub-circuits; N is an integer greater than 1; the driving control signal generation circuit is configured to generate a driving control signal, and the driving control signal is output through the driving control signal output terminal; an nth output sub-circuit is electrically connected to the driving control signal output terminal, an nth output clock signal line and an nth driving signal output terminal respectively, the nth output sub-circuit is configured to control the nth output clock signal line to provide an nth output clock signal to the nth driving signal output terminal under the control of the driving control signal; n is a positive integer less than or equal to N.

Abstract: Disclosed is a shift register including: an input sub-circuit, an output sub-circuit and a first control sub-circuit, wherein the input sub-circuit is electrically connected to a signal input end and a pull-up node, and is configured to provide a signal to the pull-up node under the control of a signal from the signal input end; the output sub-circuit is electrically connected to a first output end, the pull-up node and a clock signal end, and is configured to provide a signal from the clock signal end to the first output end under the control of a signal from the pull-up node; and the first control sub-circuit is electrically connected to a control signal end and a signal input end, and is configured to provide a signal from the control signal end to the signal input end under the control of the signal from the control signal end.

Abstract: An array substrate includes a plurality of first wiring lines and a plurality of second wiring lines arranged on a base substrate, the first wiring lines and the second wiring lines intersect each other to define a plurality of pixel areas, each of the pixel areas comprises a transistor, a first electrode, a second electrode, a first via hole and a second via hole; an orthographic projection of the first via hole on the base substrate at least partially overlaps an orthographic projection of the first electrode on the base substrate, and an orthographic projection of the second via hole on the base substrate at least partially overlaps the orthographic projection of the first electrode on the base substrate; the orthographic projection of the first via hole on the base substrate does not overlap an orthographic projection of the second electrode on the base substrate.

Abstract: A shift-register unit, a grid driving circuit and a displaying device, which relates to the technical field of displaying. In the present disclosure, the oxide-semiconductor layers of the oxide thin-film transistors may be delimited into regions according to the total channel widths and the channel lengths required by the oxide thin-film transistors in the shift-register unit, wherein the sum of the widths of the independent semiconductor branches obtained by the delimitation is equal to the required total channel width. Accordingly, one oxide thin-film transistor can realize the required total channel width by using the one or more semiconductor branches, to ensure the normal operation of the oxide thin-film transistor, whereby the oxide-semiconductor layers of the different oxide thin-film transistors can be configured differently, to realize the purpose of reducing the border frame of the displaying device.

Abstract: An array substrate (ARR) includes a base substrate (BP), a first electrode layer (EDLA), an insulating layer (PVX) and a second electrode layer (EDLB) stacked in sequence; where one of the first electrode layer (EDLA) and the second electrode layer (EDLB) is provided with a slit electrode (SLD); the array substrate (ARR) further includes a plurality of data lines (DataL), and a part of the data lines (DataL) adjacent to the slit electrode (SLD) extends linearly along a column direction (DV); the slit electrode (SLD) is provided with a plurality of slits (SL), the slits (SL) include a first slit section (SLA), and an angle between an extending direction of the first slit section (SLA) and a row direction (DH) is in a range of 69° to 85°.

Abstract: A display substrate and a display apparatus are provided. The display substrate includes a base substrate, and gate lines and data lines cross with each other to define pixel units. Each pixel unit includes a first transistor and a second transistor, an active layer of the first transistor includes a first contact portion and a second contact portion, an active layer of the second transistor includes a third contact portion and a fourth contact portion, the first contact portion is electrically connected to the corresponding data line, the second contact portion is electrically connected to the third contact portion, and the fourth contact portion is electrically connected to the first electric pole. Along the second direction, a maximum distance between the first contact portion and the corresponding gate line is not less than a maximum distance between the fourth contact portion and the same gate line.

Abstract: A liquid crystal aligning agent includes polymer(s) from at least one of polyamic acid and group of polyimides by ring closure thereof. The acid includes a first segment structure formed by first dianhydride of formula (I) and first diamine of formula (II) or (III). X1 is an amorphous first soft segment. L is single bond, double bond, divalent or trivalent hydrocarbon group having 1 to 3 Cs. Y1 is single bond, O, NH, S, unsaturated double bond(s), or aliphatic, aromatic, heterocyclic or fused ring. One A1 and one A2, combined with Y1, are each C. Remaining A1s and A2s are each CH, CR or N. Z1 is aliphatic, aromatic, heterocyclic or fused ring. A3s and A4s are each CH, CR or N. Neither of numbers of Ns in the A1s, A2s, A3s and A4s is more than two, R1, R2 and R are each hydrogen or aliphatic hydrocarbon group.

Abstract: According to an embodiment of the disclosure, a method, apparatus, device, and storage medium for session interaction is provided. The method includes receiving a selection of one or more target digital assistants in a target session by a user, the one or more target digital assistants being not members of the target session, and members of the target session comprising a plurality of digital assistants; presenting a first message sent by the user in the target session; and presenting one or more reply messages for the first message sent by the one or more target digital assistants, respectively. Therefore, the user can select a digital assistant that does not belong to the session to reply to the message sent by the user, thereby improving convenience of interaction between the user and the digital assistant.

Abstract: A method of operating a communication device includes amplifying a preset proportion of symbols in a set of input symbols to generate a set of amplified symbols, accumulating the set of amplified symbols to generate an enhanced symbol, searching for a first path according to the enhanced symbol, accumulating unamplified symbols in the set of input symbols to generate an normal symbol, and searching for the first path according to the normal symbol. The method further includes generating a first path signal if the first path is found according to the enhanced symbol and/or the normal symbol, and generating a first path dynamic range (FPDR) according to at least the first path signal.

Abstract: A method for enhancing timing performance of ultra-wideband (UWB) ranging with aid of phase detection and associated apparatus such as a communication circuit and an electronic device are provided. The method may include: utilizing a time coarse estimation circuit within a UWB ranging processing circuit to perform time coarse estimation according to a UWB signal to generate at least one time estimation result; and utilizing a time fine estimation circuit within the UWB ranging processing circuit to perform time fine estimation according to the at least one time estimation result to generate an estimated time; where the time coarse estimation circuit performs the phase detection according to a feature database within the communication circuit and at least one feature obtained from the UWB signal, to generate at least one fractional part of the at least one time estimation result, for enhancing time accuracy in advance to enhance the timing performance.

Abstract: The present disclosure provides a satellite network deterministic route construction method, forwarding method, and system. The deterministic route construction method includes: according to service data and topology information of an entire satellite network, searching for a plurality of feasible paths from the source node to the destination node corresponding to the service data; according to transmission configuration information of the service data and the topology information of the entire satellite network, screening out, from the plurality of feasible paths, a feasible path satisfying a preset transmission demand as present target feasible path; and determining path overhead of each target feasible path, and selecting a feasible path with lowest path overhead as a deterministic forwarding path of the service data.

Abstract: A display substrate is provided to include a base substrate including an active display region and a dummy region, the dummy region includes at least one first dummy sub-region arranged in a first direction together with the active display region; active gate lines in the active display region and extending along the first direction, at least one end of at least one active gate line extends into a first dummy sub-region on the same side as the at least one end; and at least one dummy data line within the first dummy sub-region and extending along a second direction; an orthographic projection of an end of the at least one active gate line in the first dummy sub-region on the base substrate does not overlap with an orthographic projection of any dummy data line on the base substrate. A display panel and a display apparatus are further provided.

Abstract: Provided is display panel. The display panel includes: a base substrate; multiple first signal traces, multiple second signal traces, multiple pixel circuits arranged in an array, multiple pixel electrodes corresponding to the plurality of pixel circuits, a common electrode provided with multiple first openings corresponding to the plurality of pixel circuits, and a black matrix layer, wherein an orthographic projection of each first opening on the base substrate covers orthographic projections of the first connection position, the second connection position, and the third connection position of the pixel circuit corresponding to the first opening on the base substrate, and an orthographic projection of the black matrix layer on the base substrate covers orthographic projections of the first openings on the base substrate.

Abstract: In various embodiments, a training application trains a machine learning model to modify portions of shapes when designing 3D objects. The training application converts first structural analysis data having a first resolution to first coarse structural analysis data having a second resolution that is lower than the first resolution. Subsequently, the training application generates one or more training sets based on a first shape, the first coarse structural analysis data, and a second shape that is derived from the first shape. Each training set is associated with a different portion of the first shape. The training application then performs one or more machine learning operations on the machine learning model using the training set(s) to generate a trained machine learning model. The trained machine learning model modifies at least a portion of a shape having the first resolution based on coarse structural analysis data having the second resolution.

Abstract: A multiplexer circuit, a multiplexing module, a display device and a driving method are provided. The multiplexer circuit is electrically coupled to M data voltage providing ends and a plurality of data lines. The multiplexer circuit includes N multiplexing control lines and N multiplexing circuits, an nth multiplexing circuit includes M multiplexing sub-circuits, and an nth multiplexing control line includes M control lines. An mth multiplexing sub-circuit included in an nth multiplexing circuit is electrically coupled to an mth control line in the nth multiplexing control line, an mth data voltage providing end and a corresponding data line, and configured to write a data voltage provided by the mth data voltage providing end into the corresponding data line under the control of a control signal provided by the mth control line.

Abstract: Provided is an electrostatic discharge circuit. The electrostatic discharge circuit includes a first transistor, a second transistor, and a third transistor. A gate and a first electrode of the first transistor are coupled to a first node, the first node being coupled to a signal line, and a second electrode of the first transistor is coupled to a second node; a gate and a first electrode of the second transistor are both coupled to a third node, the third node being coupled to an electrostatic protection line, and a second electrode of the second transistor is coupled to a fourth node, the fourth node being coupled to the second node; a gate of the third transistor is coupled to the second node, a first electrode of the third transistor is coupled to the first node, and a second electrode of the third transistor is coupled to the third node.

Abstract: The present disclosure provides methods and apparatuses for spontaneous text-to-speech (TTS) synthesis. A target text may be obtained. A fluency reference factor may be determined based at least on the target text. An acoustic feature corresponding to the target text may be generated with the fluency reference factor. A speech waveform corresponding to the target text may be generated based on the acoustic feature.

Abstract: The present disclosure provides an information acquiring method and apparatus, and an attention degree detecting system. The information acquiring method includes: acquiring a video frame captured by a video capturing equipment detecting whether a pedestrian exists in the video frame by using a first deep-learning model; processing the video frame by using a second deep-learning model to generate a pedestrian bounding box of the pedestrian under a condition that the pedestrian exists in the video frame, and assigning a corresponding pedestrian identifier to the pedestrian bounding box; identifying an image in the pedestrian bounding box by using a third deep-learning model to identify feature information of the pedestrian; and writing a pedestrian historical data into a database, wherein the pedestrian historical data comprises a timestamp and an identifier of the video frame, coordinate information of the pedestrian bounding box, the pedestrian identifier and the feature information of the pedestrian.

Abstract: The present disclosure provides a liquid crystal writing board and a method for repairing the same. The liquid crystal writing board includes a first substrate, a second substrate, and a bistable liquid crystal layer disposed between the first substrate and the second substrate. The first substrate includes a plurality of first signal line groups, the first signal line group including at least two first signal lines; a plurality of second signal lines, the first signal lines and the second signal lines intersecting with each other; and a control electrode disposed in an area surrounded by two adjacent first signal lines and two adjacent second signal lines, the first signal lines and the second signal lines being configured to jointly provide control signals to the control electrode. The first signal lines in the first signal line group are electrically connected with each other.