Abstract: A method for imparting flame retardancy to a substrate material. The method comprises adding to a substrate material a flame retardant composition. The flame retardant composition comprises at least one flame retardant salt, a nitrogen-containing compound, and optionally water. The at least one flame retardant salt comprises an ammonium salt of phosphoric acid. The ammonium salt of phosphoric acid comprises water soluble ammonium polyphosphate (APP). The water soluble ammonium polyphosphate has a total nitrogen as N from about 5 to about 15 weight percent, and a total phosphorus as P2O5 from about 30 to about 40 weight percent, based on the total weight of the ammonium polyphosphate (APP).

Abstract: A method for imparting flame retardancy to a substrate material. The method comprises adding to a substrate material a flame retardant composition. The flame retardant composition comprises at least one flame retardant salt, a nitrogen-containing compound, and optionally water. The at least one flame retardant salt comprises an ammonium salt of phosphoric acid. The ammonium salt of phosphoric acid comprises water soluble ammonium polyphosphate (APP). The water soluble ammonium polyphosphate has a total nitrogen as N from about 5 to about 15 weight percent, and a total phosphorus as P2O5 from about 30 to about 40 weight percent, based on the total weight of the ammonium polyphosphate (APP).

Abstract: A process for preparing a flame retardant composition, the process comprising: adding to a container at least one flame retardant salt, a nitrogen-containing compound, and optionally water; and mixing the contents of the container to give a dispersed mixture or dissolved solution comprising the flame retardant composition; wherein the at least one flame retardant salt comprises an ammonium salt of phosphoric acid; wherein the ammonium salt of phosphoric acid comprises water soluble ammonium polyphosphate (APP); wherein the water soluble ammonium polyphosphate has a total nitrogen as N from about 5 to about 15 weight percent, and a total phosphorus as P2O5 from about 30 to about 40 weight percent, based on the total weight of the ammonium polyphosphate (APP).

Abstract: A process for preparing a flame retardant composition, the process comprising: adding to a container at least one flame retardant salt, a nitrogen-containing compound, and optionally water; and mixing the contents of the container to give a dispersed mixture or dissolved solution comprising the flame retardant composition; wherein the at least one flame retardant salt comprises an ammonium salt of phosphoric acid; wherein the ammonium salt of phosphoric acid comprises water soluble ammonium polyphosphate (APP); wherein the water soluble ammonium polyphosphate has a total nitrogen as N from about 5 to about 15 weight percent, and a total phosphorus as P2O5 from about 30 to about 40 weight percent, based on the total weight of the ammonium polyphosphate (APP).

Abstract: This disclosure provides a composition comprising one or more substrate materials (e.g., polymers, rubbers, paper pulps, textiles, or polymer foams) and a flame retardant composition. The flame retardant composition includes at least one flame retardant salt (e.g., an ammonium salt of phosphoric acid such as water soluble ammonium polyphosphate), a nitrogen-containing compound (e.g., urea), and optionally water. This disclosure also provides a process for preparing the flame retardant composition, a process for imparting flame retardancy to a substrate material, and an intumescent process for forming an insulating protective layer on a substrate. This disclosure further provides fire retardant articles and processes for preparing fire retardant articles.

Abstract: This disclosure provides a composition comprising one or more substrate materials (e.g., polymers, rubbers, paper pulps, textiles, or polymer foams) and a flame retardant composition. The flame retardant composition includes at least one flame retardant salt (e.g., an ammonium salt of phosphoric acid such as water soluble ammonium polyphosphate), a nitrogen-containing compound (e.g., urea), and optionally water. This disclosure also provides a process for preparing the flame retardant composition, a process for imparting flame retardancy to a substrate material, and an intumescent process for forming an insulating protective layer on a substrate. This disclosure further provides fire retardant articles and processes for preparing fire retardant articles.

Abstract: An integrated circuit is provided having a base with a first dielectric layer formed thereon. A second dielectric layer is formed over the first dielectric layer. A third dielectric layer is formed in spaced-apart strips over the second dielectric layer. A first trench opening is formed through the first and second dielectric layers between the spaced-apart strips of the third dielectric layer. A second trench opening is formed contiguously with the first trench opening through the first dielectric layer between the spaced-apart strips of the third dielectric layer. Conductor metals in the trench openings form self-aligned trench interconnects.

Abstract: An integrated circuit and manufacturing method therefor is provided having a base with a first dielectric layer formed thereon. A second dielectric layer is formed over the first dielectric layer. A third dielectric layer is formed in spaced-apart strips over the second dielectric layer. A first trench opening is formed through the first and second dielectric layers between the spaced-apart strips of the third dielectric layer. A second trench opening is formed contiguously with the first trench opening through the first dielectric layer between the spaced-apart strips of the third dielectric layer. Conductor metals in the trench openings form self-aligned trench interconnects.

Abstract: A gate structure having associated (LDD) regions and source and drain is formed as is conventional. A first oxide spacer, for example, is formed along the sidewalls of the gate structure. A layer of metal such as titanium is then deposited over the surface of the gate structure. Second sidewall spacers are formed covering the metal over the first sidewall spacer and covering the metal over isolation regions. A layer of polysilicon is deposited over the surface of the gate structure. A rapid thermal annealing (RTA) is performed causing the metal to react with both the silicon in the junction below the metal and the polysilicon above the metal forming a metal silicide. Metal along the sidewalls between the first and second sidewall spacers and over the isolation regions does not react and is etched away. By providing an additional source of silicon in the polysilicon layer above the metal, a thicker silicide is achieved.

Abstract: A silicon-on-insulator semiconductor device is provided in which a single wafer die contains a transistor over an insulator layer to form a fully depleted silicon-on-insulator device and a transistor formed in a semiconductor island over an insulator structure on the semiconductor wafer forms a partially depleted silicon-on-insulator device.

Abstract: A method of fabricating first and second gates comprising the following steps. A substrate having a gate dielectric layer formed thereover is provided. The substrate having a first gate region and a second gate region. A thin first gate layer is formed over the gate dielectric layer. The thin first gate layer within the second gate region is masked to expose a portion of the thin first gate layer within the first gate region. The exposed portion of the thin first gate layer is converted to a thin third gate layer portion. A second gate layer is formed over the thin first and third gate layer portions. The second gate layer and the first and third gate layer portions are patterned to form a first gate within first gate region and a second gate within second gate region.

Abstract: A method of fabricating an ultra-small semiconductor structure comprising the following steps. A substrate having a lower dielectric layer and an overlying upper dielectric layer formed thereover is provided. Using a lithography process having a lithography limit, the upper dielectric layer is patterned to form a first opening exposing a portion of the lower dielectric layer. The first opening having exposed side walls and a width equal to the lithography limit. Sidewall spacers having a lower width are formed over the exposed side walls of the first opening. Using the sidewall spacers as masks, the lower dielectric layer is patterned to form a lower opening having a width less than the first opening width. The patterned upper dielectric layer is removed. An ultra-small semiconductor structure is formed within the lower opening. The ultra-small semiconductor structure having a width equal to the lithography limit minus twice the lower width of the sidewall spacer.

Abstract: A method for forming a transistor having an elevated source/drain structure is described. A gate electrode is formed overlying a substrate and isolated from the substrate by a gate dielectric layer. Isolation regions are formed in and on the substrate wherein the isolation regions have a stepped profile wherein an upper portion of the isolation regions partly overlaps and is offset from a lower portion of the isolation regions in the direction away from the gate electrode. Ions are implanted into the substrate between the gate electrode and the isolation regions to form source/drain extensions. Dielectric spacers are formed on sidewalls of the gate electrode and the isolation regions.

Abstract: A method of fabricating first and second gates comprising the following steps. A substrate having a gate dielectric layer formed thereover is provided. The substrate having a first gate region and a second gate region. A thin first gate layer is formed over the gate dielectric layer. The thin first gate layer within the second gate region is masked to expose a portion of the thin first gate layer within the first gate region. The exposed portion of the thin first gate layer is converted to a thin third gate layer portion. A second gate layer is formed over the thin first and third gate layer portions. The second gate layer and the first and third gate layer portions are patterned to form a first gate within first gate region and a second gate within second gate region.

Abstract: A method for forming a MOSFET having an elevated source/drain structure is described. A sacrificial oxide layer is provided on a substrate. A polish stop layer is deposited overlying the sacrificial oxide layer. An oxide layer is deposited overlying the polish stop layer. An opening is formed through the oxide layer and the polish stop layer to the sacrificial oxide layer. First polysilicon spacers are formed on sidewalls of the opening wherein the first polysilicon spacers form an elevated source/drain structure. Second polysilicon spacers are formed on the first polysilicon spacers. The oxide layer and sacrificial oxide layer exposed within the opening are removed. An epitaxial silicon layer is grown within the opening. A gate dielectric layer is formed within the opening overlying the second polysilicon spacers and the epitaxial silicon layer. A gate material layer is deposited within the opening.

Abstract: A method for forming a transistor having an elevated source/drain structure is described. A gate electrode is formed overlying a substrate and isolated from the substrate by a gate dielectric layer. Isolation regions are formed in and on the substrate wherein the isolation regions have a stepped profile wherein an upper portion of the isolation regions partly overlaps and is offset from a lower portion of the isolation regions in the direction away from the gate electrode. Ions are implanted into the substrate between the gate electrode and the isolation regions to form source/drain extensions. Dielectric spacers are formed on sidewalls of the gate electrode and the isolation regions.

Abstract: A method for forming a single gate having a dual work-function is described. A gate electrode is formed overlying a gate dielectric layer on a substrate. Sidewalls of the gate electrode are selectively doped whereby the doped sidewalls have a first work-function and whereby a central portion of the gate electrode not doped has a second work-function to complete formation of a single gate having multiple work-functions in the fabrication of integrated circuits.

Abstract: A method for forming a thicker silicide over a MOS device is described. This is achieved using a process where the gate structure is formed by conventional techniques upon a substrate. A low-energy implantation is performed to form lightly doped source and drain (LDD) regions in the substrate in the areas not protected by the gate structure. A first spacer composed of tetraethyl-oxysilane (TEOS oxide), for example, is formed along the sidewalls of the gate structure. A second low-energy implantation is performed to form the source and drain (S/D) in the areas not protected by the gate structure and first spacer. A layer of metal such as titanium (Ti), for example, is then deposited over the surface of the gate structure. A second sidewall spacer composed of titanium nitride (TiN), for example, is formed along the sidewalls of the gate structure covering the metal over the first sidewall spacer and covering the metal over isolation regions.

Abstract: An integrated circuit and manufacturing method therefor is provided having a base with a first dielectric layer formed thereon. A second dielectric layer is formed over the first dielectric layer. A third dielectric layer is formed in spaced-apart strips over the second dielectric layer. A first trench opening is formed through the first and second dielectric layers between the spaced-apart strips of the third dielectric layer. A second trench opening is formed contiguously with the first trench opening through the first dielectric layer between the spaced-apart strips of the third dielectric layer. Conductor metals in the trench openings form self-aligned trench interconnects.

Abstract: A method to form SOI devices using wafer bonding. A first substrate is provided having trenches in a first side. A first insulating layer is formed over the first side of the first substrate and filling the trenches. We planarize the first insulating layer to form isolation regions (e.g., STI). The three embodiments of the invention planarize the first insulating layer to different levels. In the second embodiment, the first insulating layer is etched back to form a recess. This recess later forms an air gap. We provide a second substrate having a second insulating layer over a first side of the second substrate. We bond the second insulating layer to the first insulating layer. Next, we thin the first substrate from the second side to expose the first insulating layer to form active areas between the isolation regions. Lastly, devices are formed in and on the active areas.