Abstract: A method for siliciding source/drain junctions is described wherein compressive stress of the underlying silicon is avoided by the insertion of a buffer layer between the silicide and the silicon. A gate electrode and associated source/drain extensions are provided in and on a semiconductor substrate. A buffer oxide layer is deposited overlying the semiconductor substrate and the gate electrode. A polysilicon layer is deposited overlying the buffer oxide layer. The polysilicon layer will form the source/drain junctions and silicon source. The source/drain junctions are silicided whereby the buffer oxide layer provides compressive stress relief during the siliciding.

Abstract: A method for fabricating a metal-insulator-metal capacitor wherein top metal corner shaping during patterning is eliminated is described. An insulating layer is provided overlying a semiconductor substrate. A first metal layer is deposited over the insulating layer. A capacitor dielectric layer is deposited overlying the first metal layer. A second metal layer is deposited overlying the capacitor dielectric layer and patterned to form a top metal electrode. A flowable material layer is deposited overlying the capacitor dielectric and the top metal electrode and anisotropically etched away to leave spacers on sidewalls of the top metal electrode. A photoresist mask is formed overlying the capacitor dielectric and the top metal electrode wherein the spacers provide extra photoresist thickness at the sidewalls of the top metal layer.