Abstract: A device has a semiconductor chip comprising a substrate and an integrated circuit, a metal stack of metal layers connected to the semiconductor chip, and a planar spiral inductor comprising at least two metal layers of the metal stack, wherein the semiconductor chip defines a semiconductor plane having a semiconductor plane normal vector and the planar spiral inductor defines a inductor plane having an inductor plane normal vector, wherein an angle between the semiconductor plane normal vector and the inductor plane normal vector is between 1 and 90 degrees, a sensing membrane when interacting with an ionized fluid is operable to attract ions, wherein the sensing membrane is operable to electrically communicate with the planar spiral inductor; and a fluid property measurement circuit operable to measure a quality factor or inductance of the planar spiral inductor and output a fluid property signal.

Abstract: A device has a CMOS metal stack of metal layers oriented substantially horizontally, and an inductor coil oriented substantially vertically in the CMOS metal stack and comprising at least two metal layers of the CMOS metal stack. A device has a semiconductor chip comprising a substrate and an integrated circuit, a metal stack of metal layers, a planar spiral inductor comprising at least two metal layers of the metal stack, wherein the semiconductor chip defines a semiconductor plane having a semiconductor plane normal vector and the planar spiral inductor defines an inductor plane having a inductor plane normal vector, wherein an angle between the semiconductor plane normal vector and the inductor plane normal vector is between 1 and 90 degrees.

Abstract: An apparatus, system, and method for the manufacturing of an inductor using deep trench isolation (DTI) is disclosed. The apparatus may include a doped substrate forming a well. The apparatus may also include a trench etched in the substrate. The trench may have a shape of a coil. The apparatus may additionally include a dielectric in the trench. The apparatus may further include a conductor within the dielectric in the trench. The dielectric and the conductor may create a first inductor.

Abstract: Aspects provide a device comprising: a substrate doped to form a first well; a first deep trench etched in the substrate; a dielectric in the first deep trench; a first conductor within the dielectric in the first deep trench and biased to create a first depletion region in the substrate proximate the first deep trench, wherein the substrate forms a bottom electrode of a first deep trench isolation varactor and the conductor in the first deep trench forms a top electrode of the first deep trench isolation varactor; a sense electrode operable to become electrically charged when interacting with an ionized fluid, wherein the sense electrode is operable to electrically charge the first deep trench isolation varactor; and a fluid property measurement circuit operable to determine a change in the capacitance of the first deep trench isolation varactor and output a fluid property signal.

Abstract: Aspects provide fluid ion sensing via inductors using deep trench isolation, comprising: a coil-shaped deep trench etched in a substrate, a dielectric in the deep trench, a conductor within the dielectric in the deep trench, wherein the conductor forms a deep trench inductor, a sense electrode operable to become electrically charged when interacting with an ionized fluid, wherein the sense electrode is operable to electrically communicate with the deep trench inductor, and a fluid property measurement circuit operable to measure a quality factor or inductance of the deep trench inductor and output a fluid property signal.

Abstract: Inductors and biased deep trench isolation (DTI) varactors may detect the type and concentration of ions in a fluid. An ion sensing device comprises: a deep trench isolation varactor in a substrate having a dielectric and a conductor and biased to create a depletion region in the substrate proximate the deep trench; a sense electrode operable to become electrically charged when interacting with an ionized fluid, wherein the sense electrode is operable to electrically charge the deep trench isolation varactor; an inductor proximate the deep trench isolation varactor and configured so that a change of a characteristic of the deep trench isolation varactor induces a change in the quality factor of the inductor; and a fluid property measurement circuit operable to determine a change in the quality factor of the inductor and output a fluid property signal.

Abstract: An apparatus, system, and method for the manufacturing of an inductor having a high quality factor using deep trench isolation (DTI) is disclosed. The apparatus may include a substrate doped to form a well. The apparatus may also include an inductor coil above a surface of the substrate. The apparatus may further include a trench etched in the substrate, a dielectric in the trench, and a conductor within the dielectric in the trench. The conductor may be biased to create a depletion region below the inductor coil.

Abstract: An apparatus, system, and method for the manufacturing of a varactor using deep trench isolation (DTI) is disclosed. The apparatus may include a substrate doped to form a well. The apparatus may also include a first trench etched in the substrate. The apparatus may additionally include a second trench etched in the substrate parallel to the first trench. The apparatus may further include a dielectric in the first trench and the second trench and a conductor within the dielectric in the first trench and the second trench. The substrate may form a bottom electrode of a first varactor and a second varactor. The conductor in the first trench may form a top electrode of the first varactor. The conductor in the second trench may form a top electrode of the second varactor.

Abstract: Systems and methods for determining an operational limit for a circuit component are disclosed. The system may include an operational limit generation system including instructions stored in non-transitory computer-readable medium and executable by a processor to receive input parameters related to a component, perform an age-dependent analysis of the component based on the input parameters, and determine an operational limit for the component based on a result of the age-dependent analysis of the component. The age-dependent analysis may include performing a non-aging simulation of the component and a plurality of aging simulations of the component including a simulation of an aging operation of the component based on aging conditions specified by the input parameters, a different value of at least one operational parameter of the component, and effects of self-heating on aging conditions of the component, and comparing results of the aging simulations with a result of the non-aging simulation.

Abstract: A non-transitory computer-readable medium comprising instructions executable by a processor to receive a set of input parameters related to a circuit component and perform an age-dependent analysis of the circuit component based on the set of input parameters. The age-dependent analysis of the circuit component includes performing a series of automated simulations of a non-aged model of the circuit component using each of multiple values of a first operational parameter, performing a series of automated simulations of an aged model of the circuit component using each of the multiple values of the first operational parameter, and comparing respective results of the automated simulations of the non-aged and aged models of the circuit component. The instructions are further executable to determine an operational limit for the circuit component based at least on the age-dependent analysis of the circuit component.

Abstract: An electronic package includes a first integrated circuit (IC) die arranged in a first orientation, a second IC die arranged in a second orientation inverted relative to the first orientation, at least one upper conductive routing layer extending over the first IC die and second IC die, at least one lower conductive routing layer extending under the first IC die and second IC die, and a mold compound at least partially encapsulating the first IC die and the second IC die.

Abstract: A capacitor structure may include a lower conducting layer (e.g., poly 1 layer) and an upper conducting layer (e.g., overlying poly 2 layer), which define an anode and cathode, and a dielectric layer (e.g., an ONO layer stack) located between the upper conducting layer and the lower conducting layer, wherein a portion of the dielectric layer (e.g., at least the nitride layer of the ONO layer stack) extends beyond a lateral edge of the upper conducting layer. A method forming such capacitor structure may utilize a spacer adjacent the lateral edge of the upper conducting layer and over the first portion of the dielectric layer, performing an etch to remove a first portion of the dielectric layer but protect a second portion located below the spacer and extending laterally beyond an edge of the upper conducting layer.

Abstract: The teachings of the present disclosure may be applied to the manufacture and design of capacitors. In some embodiments of these teachings, a capacitor may be formed on a heavily doped substrate. For example, a method for manufacturing a capacitor may include: depositing an oxide layer on a first side of a heavily doped substrate; depositing a first metal layer on the oxide layer; and depositing a second metal layer on a second side of the heavily doped substrate.

Abstract: A capacitor structure may include a lower conducting layer (e.g., poly 1 layer) and an upper conducting layer (e.g., overlying poly 2 layer), which define an anode and cathode, and a dielectric layer (e.g., an ONO layer stack) located between the upper conducting layer and the lower conducting layer, wherein a portion of the dielectric layer (e.g., at least the nitride layer of the ONO layer stack) extends beyond a lateral edge of the upper conducting layer. A method forming such capacitor structure may utilize a spacer adjacent the lateral edge of the upper conducting layer and over the first portion of the dielectric layer, performing an etch to remove a first portion of the dielectric layer but protect a second portion located below the spacer and extending laterally beyond an edge of the upper conducting layer.

Abstract: The teachings of the present disclosure may be applied to the manufacture and design of capacitors. In some embodiments of these teachings, a capacitor may be formed on a heavily doped substrate. For example, a method for manufacturing a capacitor may include: depositing an oxide layer on a first side of a heavily doped substrate; depositing a first metal layer on the oxide layer; and depositing a second metal layer on a second side of the heavily doped substrate.

Abstract: At least one high voltage rated isolation capacitor is formed on a face of a primary integrated circuit die. The isolation capacitor AC couples the primary integrated circuit in a first voltage domain to a second integrated circuit in a second voltage domain. The isolation capacitor DC isolates the primary integrated circuit from the second integrated circuit die.

Abstract: High voltage rated isolation capacitors are formed on a face of a primary integrated circuit die. The isolation capacitors AC couple the primary integrated circuit in a first voltage domain to a second integrated circuit in a second voltage domain. The isolation capacitors DC isolate the primary integrated circuit from the second integrated circuit die. Isolated power transfer from the first voltage domain to the second voltage domain is provided through the high voltage rated isolation capacitors with an AC oscillator or PWM generator. The AC oscillator voltage amplitude may be increased for an increase in power through the high voltage rated isolation capacitors, and a larger value capacitor in the second voltage domain may provide for peak current demand from circuits in the second voltage domain.

Abstract: A semiconductor chip for process monitoring of semiconductor fabrication, has a plurality of arrays with a plurality of diodes, each diode being formed in the chip, each diode being associated with a stack with at least one horizontal interconnect, the stack and the diode connected in series to form a diode stack combination, wherein the horizontal interconnect has a salicided polysilicon interconnect comprising complementary doped polysilicon sections to form a reverse biased diode.

Abstract: A semiconductor chip for process monitoring of semiconductor fabrication, has a plurality of arrays with a plurality of diodes, each diode being formed in the chip, each diode being associated with a stack with at least one horizontal interconnect, the stack and the diode connected in series to form a diode stack combination, wherein the horizontal interconnect has a salicided polysilicon interconnect comprising complementary doped polysilicon sections to form a reverse biased diode.

Abstract: At least one high voltage rated isolation capacitor is formed on a face of a primary integrated circuit die. The isolation capacitor AC couples the primary integrated circuit in a first voltage domain to a second integrated circuit in a second voltage domain. The isolation capacitor DC isolates the primary integrated circuit from the second integrated circuit die.