Abstract: A method is described to form a MOSFET with a fully silicided gate electrode and fully silicided, raised S/D elements that are nearly coplanar to allow a wider process margin when forming contacts to silicided regions. An insulator block layer is formed over STI regions and a conformal silicidation stop layer such as Ti/TiN is disposed on the insulator block layer and active region. A polysilicon layer is deposited on the silicidation stop layer and is planarized by a CMP process to form raised S/D elements. An oxide hardmask on the gate electrode is removed to produce a slight recess between the spacers. A silicidation process yields a gate electrode and raised S/D elements comprised of NiSi. Optionally, a recess is formed in the substrate between an insulator block mask and spacer and a Schottky barrier is used instead of a silicidation stop layer to form a Schottky Barrier MOSFET.

Abstract: This invention describes a method of stacking, bonding, and electrically interconnecting a plurality of thin integrated circuit wafers to form an interconnected stack of integrated circuit layers. The first integrated circuit layer is formed by conventional processing on a silicon wafer to the stage where bond pads are patterned on a wiring layer interconnecting the subjacent semiconductive devices. The remaining integrated circuit layers are formed by first processing a standard wafer to form integrated circuit devices and wiring levels up to but not including bond pads. Each of these wafers is mounted onto a handler wafer by its upper face with a sacrificial bonding agent. The wafer is thinned, permanently fastened to the top surface of the first base wafer by a non-conductive adhesive applied to the thinned under face, and dismounted from the handler. Vertical openings are etched through the thinned layer to the bond pads on the subjacent wafer.

Abstract: A wafer is provided having through-holes therein to form a through-hole via wafer. A substrate of a sacrificial wafer is provided. The substrate is coated with a polymer having low adhesion to metals. A conductive layer is deposited on the polymer. A photoresist layer is coated on the conductive layer. The through-hole via wafer is bonded to the sacrificial wafer wherein the photoresist layer provides the bonding. The photoresist exposed in the through-holes is developed away to expose the conductive layer. The through-holes are filled with a conductive material by electroplating the conductive layer. The photoresist is stripped in an ultrasonic bath wherein the photoresist separates from the through-hole wafer and wherein the filled through-holes separate from the polymer at an interface between the polymer and the conductive layer to complete separation of the through-hole via wafer from the sacrificial wafer.

Abstract: A new method to form shielded vias with microstrip ground plane in the manufacture of an integrated circuit device is achieved. The method comprises, first, providing a substrate. The substrate is etched through to form holes for planned shielded vias with microstrip ground plane. A first dielectric layer is formed overlying the top side of the substrate and lining the holes. A first conductive layer is deposited overlying the first dielectric layer and lining the holes. A second dielectric layer is deposited overlying the first conductive layer and lining the holes. A second conductive layer is deposited overlying the second dielectric layer and filling the holes. The second conductive layer is planarized to confine the second conductive layer to the holes and to thereby complete the shielded vias with microstrip ground plane. Silicon carrier modules and stacked, multiple integrated circuit modules are formed using shielded vias with microstrip ground plane to improve RF performance.

Abstract: Method of fabricating a micro-mirror switching device in single crystal silicon are described. The device is fabricated as three main elements: silicon mirror plate with metal-mirror, secondary actuator, and hinge/spring mechanism to integrate the mirror plate with the actuator. p-n junction is first formed on p-type silicon. Trenches are then etched in n-silicon to define the device element boundaries and filled with silicon dioxide. Three layers of sacrificial oxide and two structural poly-silicon layers are deposited and patterned to form device elements. Novel release processes, consisting of backside electrochemical etching in potassium-hydroxide, reactive ion etching to expose oxide-filled trenches from the bottom, and hydrofluoric acid etching of sacrificial oxide layers and oxide in silicon trenches, form the silicon blocks; those that are not attached to structural poly-silicon are sacrificed and those that are attached are left in place to hold together the switching device elements.

Abstract: A method for forming wafers having through-wafer vias for wafer-level packaging of devices, the method comprising the steps of depositing metal on one of two wafers; bonding the two wafers using the metal deposited on the one of the two wafers; forming a through-wafer via in one of the two wafers; filling the through-wafer via with a conductive material; and forming a cavity in the one of the two wafers having the through-wafer via wherein the cavity is superposable over a device.

Abstract: Inter-connectors are typically used for interconnecting electronic components. Interconnections between electronic components are generally classified into at least two broad categories of “relatively permanent” and “readily demountable”. A “readily demountable” connector includes a spring-like contact structure of one electronic component for connecting to a terminal of another electronic component. The spring-like contact structure, also known as an inter-connector, generally requires a certain amount of contact force to effect reliable pressure contact to a terminal of an electronic component. Therefore, the shape and metallurgy of the inter-connector are important factors in determining the effectiveness of the inter-connector for making pressure connection to a terminal of the electronic component. Conventional methods of making such an inter-connector use lithographic and planarisation methods to “make” the inter-connectors in segments.

Abstract: Method and apparatus for etching a tapered trench in a layer of material with a highly controllable wall profile. The layer of material has a mask adjacent a surface thereof having an opening which defines a location on the layer of material at which the trench is to be formed. Vertical etch process steps and opening enlarging process steps are then performed in an alternating manner until the trench has been etched to a desired depth. The method permits very deep tapered trenches of up to 80-100 um or more to be formed in a silicon substrate or other layer of material in a highly controllable manner. The method can be incorporated into processes for manufacturing numerous devices including MEMS devices and high power RF devices such as LDMOS and VDMOS devices.

Abstract: Inter-connectors are typically used for interconnecting electronic components. Interconnections between electronic components are generally classified into at least two broad categories of “relatively permanent” and “readily demountable”. A “readily demountable” connector includes a spring-like contact structure of one electronic component for connecting to a terminal of another electronic component. The spring-like contact structure, also known as an inter-connector, generally requires a certain amount of contact force to effect reliable pressure contact to a terminal of an electronic component. Therefore, the shape and metallurgy of the inter-connector are important factors in determining the effectiveness of the inter-connector for making pressure connection to a terminal of the electronic component. Conventional methods of making such an inter-connector use lithographic and planarisation methods to “make” the inter-connectors in segments.

Abstract: A method for forming wafers having through-wafer vias for wafer-level packaging of devices, the method comprising the steps of depositing a metal layer on one of a first wafer and a second wafer; bonding the first wafer and the second wafer using the metal layer deposited on one of the first wafer and the second wafer; forming a through-wafer via in one of the first wafer and the second wafer; filling the through-wafer via with a conductive material; and forming a cavity in the one of the first wafer and the second wafer having the through-wafer via, wherein the cavity is superposable over a device.

Abstract: Method and apparatus for fluid-based cooling of heat-generating devices are disclosed. A heat-generating device is mounted on a carrier. The heat-generating device is spatially displaced from the surface of the carrier, thereby forming a channel. The heat-generating device and the carrier are enclosed in an enclosure having an inlet and an outlet. A substantially electrically non-conductive cooling fluid for introduction into the enclosure and into the channel and expulsion from the enclosure and for extracting heat from and thereby cooling the heat-generating device and the carrier.

Abstract: A process is described for trimming photoresist patterns during the fabrication of integrated circuits for semiconductor devices and MEMS devices. A combination of a low temperature (<20° C.), high density oxygen and argon plasma and intense UV radiation is used to simultaneously trim and harden a photoresist linewidth in an ICP chamber. As an alternative, a UV hardening step can be performed in a flood exposure tool prior to the ICP plasma etch. Another option is to perform the argon plasma treatment first to harden the resist and then in a second step apply an oxygen plasma to trim the photoresist. Vertical and horizontal etch rates are decreased in a controllable manner which is useful for producing gate lengths in MOS transistors of less than 100 nm. The process can also be used to controllably increase a space width in a photoresist feature.

Abstract: An accelerometer design is described. It operates by measuring a change in capacitance when one plate is fixed and one is mobile (free to accelerate). Unlike prior art designs where such changes are caused by variations in the plate separation distance, in the design of the present invention the plate separation distance is fixed, it being the effective plate area that changes with acceleration. A key feature is that the basic unit is a pair of capacitors. The fixed plates in each case are at the same relative height but the mobile plates are offset relative to the fixed plates, one mobile plate somewhat higher than its fixed plate with the other mobile plate being somewhat lower. Then, when the mobile plates move (in the same direction), one capacitor increases in value while the other decreases by the same amount. This differential design renders the device insensitive to sources of systematic error such as temperature changes. A process for manufacturing the design is described.

Abstract: Design of a micro-mirror switching device and its fabrication in single crystal silicon are described. The device is composed of three main elements: silicon mirror plate with metal-mirror, secondary actuator, and hinge/spring mechanism to integrate the mirror plate with the actuator. p-n junction is first formed on p-type silicon. Trenches are then etched in n-silicon to define the device element boundaries and filled with silicon dioxide. Three layers of sacrificial oxide and two structural poly-silicon layers are deposited and patterned to form device elements. Novel release processes, consisting of backside electrochemical etching in potassium-hydroxide, reactive ion etching to expose oxide-filled trenches from the bottom, and hydrofluoric acid etching of sacrificial oxide layers and oxide in silicon trenches, form the silicon blocks; those that are not attached to structural poly-silicon are sacrificed and those that are attached are left in place to hold together the switching device elements.

Abstract: A process is described for trimming photoresist patterns during the fabrication of integrated circuits for semiconductor devices and MEMS devices. A combination of a low temperature (<20° C.), high density oxygen and argon plasma and intense UV radiation is used to simultaneously trim and harden a photoresist linewidth in an ICP chamber. As an alternative, a UV hardening step can be performed in a flood exposure tool prior to the ICP plasma etch. Another option is to perform the argon plasma treatment first to harden the resist and then in a second step apply an oxygen plasma to trim the photoresist. Vertical and horizontal etch rates are decreased in a controllable manner which is useful for producing gate lengths in MOS transistors of less than 100 nm. The process can also be used to controllably increase a space width in a photoresist feature.

Abstract: An accelerometer design is described. It operates by measuring a change in capacitance when one plate is fixed and one is mobile (free to accelerate). Unlike prior art designs where such changes are caused by variations in the plate separation distance, in the design of the present invention the plate separation distance is fixed, it being the effective plate area that changes with acceleration. A key feature is that the basic unit is a pair of capacitors. The fixed plates in each case are at the same relative height but the mobile plates are offset relative to the fixed plates, one mobile plate somewhat higher than its fixed plate with the other mobile plate being somewhat lower. Then, when the mobile plates move (in the same direction), one capacitor increases in value while the other decreases by the same amount. This differential design renders the device insensitive to sources of systematic error such as temperature changes. A process for manufacturing the design is described.

Abstract: An accelerometer design is described. It operates by measuring a change in capacitance when one plate is fixed and one is mobile (free to accelerate). Unlike prior art designs where such changes are caused by variations in the plate separation distance, in the design of the present invention the plate separation distance is fixed, it being the effective plate area that changes with acceleration. A key feature is that the basic unit is a pair of capacitors. The fixed plates in each case are at the same relative height but the mobile plates are offset relative to the fixed plates, one mobile plate somewhat higher than its fixed plate with the other mobile plate being somewhat lower. Then, when the mobile plates move (in the same direction), one capacitor increases in value while the other decreases by the same amount. This differential design renders the device insensitive to sources of systematic error such as temperature changes. A process for manufacturing the design is described.

Abstract: A process for fabricating an integrated circuit sensor/actuator is described. High aspect ratio deep silicon beams are formed by a process of deep trench etch and silicon undercut release etch by using oxide spacers to protect the silicon beam sidewalls during release etch. An oxide layer is then formed, followed by deposition of a controlled thickness of polysilicon which is then thermally oxidized. The polysilicon layer inside the trenches gets fully oxidized resulting in void-free trench isolation. This process creates a silicon island or beam on three sides leaving the third side for interfacing with the sensor/actuator beams. The sensor/actuator is formed by a similar process of deep trench etch and release etch process on the same substrate. These suspended beams of the sensors and actuators are bridged with the silicon islands from the fourth side. The above process finally results in suspended silicon beams connected to electrically isolated silicon islands.

Abstract: A process for manufacturing a buried oxide layer for use in partial SOI structures is described. The process begins with the etching of deep trenches into a silicon body. For a preselected depth below the surface, the inner walls of the trenches are protected and oxidation of said walls is then effected until pinch-off occurs, both inside the trenches and in the material between trenches. The result is a continuous layer of wade whose size and shape are determined by the number and location of the trenches. Application of the process to the manufacture of a partial SOI RFLDMOS structure is also described together with performance data for the resulting device.

Abstract: A process for manufacturing a buried oxide layer for use in partial SOI structures is described. The process begins with the etching of deep tenches into a silicon body. For a preselected depth below the surface, the inner walls of the trenches are protected and oxidation of said walls is then effected until pinch-off occurs, both inside the trenches and in the material between trenches. The result is a continuous layer of oxide whose size and shape are determined by the number and location of the trenches.