Patents by Inventor Ranjan J. Mathew
Ranjan J. Mathew has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7880310Abstract: A dual-mode integrated circuit comprises wirebondable and solderable electrical connectors.Type: GrantFiled: September 28, 2007Date of Patent: February 1, 2011Assignee: Intel CorporationInventor: Ranjan J. Mathew
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Publication number: 20090085201Abstract: A dual-mode integrated circuit comprises wirebondable and solderable electrical connectors.Type: ApplicationFiled: September 28, 2007Publication date: April 2, 2009Inventor: Ranjan J. Mathew
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Patent number: 7262513Abstract: A method and apparatus for making pad structures suitable for wirebonding and, optionally, also for solder-ball connections. Some embodiments include an electronics chip having a substrate with circuitry, a compliant electrically insulating layer deposited on at least a portion of the substrate, and an electrical connection pad, the pad having an electrical connection to the circuitry through an aperture in the insulating layer and a peripheral bonding zone region extending over the insulating layer. In some embodiments, the bonding zone is exclusively over the insulating layer outside of the aperture. In some embodiments, the pads are suitable for both solder-ball and wirebond connections. By making a wirebond connection to an area of a pad over the compliant insulating layer, the underlying circuitry is protected from ultrasonic energy of the bonding process.Type: GrantFiled: June 30, 2005Date of Patent: August 28, 2007Assignee: Intel CorporationInventor: Ranjan J. Mathew
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Patent number: 7102703Abstract: An improved packaged liquid crystal display (LCD) assembly is described. A recess is used to house a support material while the LCD cell 609 is positioned at least partially within the containment structure. A plurality of spaced apart stabilizers are attached from the sides of the LCD cell 609 to the substrate without transmitting residual stresses induced during fabrication and operation. A support material is dispensed in the recess such that it provides support for the LCD cell 609 without transmitting residual stresses from the substrate. The described arrangements permit an LCD assembly which minimizes the amount of forces and stresses that lead to optical defects. The stabilizers, in addition to supporting the cell, also act to contain the encapsulating material used to protect the bonding wires. The support material, in addition to minimizing transmission of stresses, also provides improved heat dissipation from the LCD cell 609.Type: GrantFiled: February 24, 1999Date of Patent: September 5, 2006Assignee: National Semiconductor CorporationInventors: Ranjan J. Mathew, Hem Takiar, Cade Murray, Tonya Fridlyand
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Patent number: 6927156Abstract: A method and apparatus for making pad structures suitable for wirebonding and, optionally, also for solder-ball connections. Some embodiments include an electronics chip having a substrate with circuitry, a compliant electrically insulating layer deposited on at least a portion of the substrate, and an electrical connection pad, the pad having an electrical connection to the circuitry through an aperture in the insulating layer and a peripheral bonding zone region extending over the insulating layer. In some embodiments, the bonding zone is exclusively over the insulating layer outside of the aperture. In some embodiments, the pads are suitable for both solder-ball and wirebond connections. By making a wirebond connection to an area of a pad over the compliant insulating layer, the underlying circuitry is protected from ultrasonic energy of the bonding process.Type: GrantFiled: June 18, 2003Date of Patent: August 9, 2005Assignee: Intel CorporationInventor: Ranjan J. Mathew
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Publication number: 20040256704Abstract: A method and apparatus for making pad structures suitable for wirebonding and, optionally, also for solder-ball connections. Some embodiments include an electronics chip having a substrate with circuitry, a compliant electrically insulating layer deposited on at least a portion of the substrate, and an electrical connection pad, the pad having an electrical connection to the circuitry through an aperture in the insulating layer and a peripheral bonding zone region extending over the insulating layer. In some embodiments, the bonding zone is exclusively over the insulating layer outside of the aperture. In some embodiments, the pads are suitable for both solder-ball and wirebond connections. By making a wirebond connection to an area of a pad over the compliant insulating layer, the underlying circuitry is protected from ultrasonic energy of the bonding process.Type: ApplicationFiled: June 18, 2003Publication date: December 23, 2004Applicant: Intel CorporationInventor: Ranjan J. Mathew
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Patent number: 6556269Abstract: A connection assembly (40) for operably coupling a plurality of independent imaging devices (41, 41;, 41″) to an optical subsystem (42). The connection assembly (40) includes a unitary flex circuit device (43) having an elongated arm portion (45), and a plurality independent finger portions (46, 46′, 46″) extending from a distal end of the arm portion (45). Each finger portion (46, 46′, 46″) defines a coupling region (47, 47′, 47″) adapted to operably couple a respective imaging device (41, 41′, 41″) to a respective finger portion (46, 46′, 46″) for support thereof. The finger portions (46, 46′, 46″) are further adapted to strategically couple each respective imaging device (41, 41′, 41″) to the optical subsystem (42) as a unit. The flex circuit device (30) includes a plurality of circuits (65) terminating at respective terminals (40) of a coupling region (47) thereof.Type: GrantFiled: March 7, 2002Date of Patent: April 29, 2003Assignee: National Semiconductor CorporationInventors: Hem P. Takiar, Ranjan J. Mathew
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Apparatus and method for substantially stress-free electrical connection to a liquid crystal display
Patent number: 6498636Abstract: A connection assembly (50) to electrically couple a transparent plate (24) of a liquid crystal display device (51) to an operating subsystem. The connection assembly (50) includes an elongated flexible tape member (52) having an elongated metallic circuit (53) which further includes a main circuit portion (55) fixedly mounted to the tape member (52), and a lead terminal (56). This terminal (56) includes a contact portion (57) adapted to electrically couple to the transparent plate (24), and a substantially flexible and movable conductive joint portion (58). The contact portion (57) and the conductive joint portion (58) electrically couple the transparent plate (24) to the circuit portion (55) of the metallic circuit (53) in a manner substantially minimizing residual stresses formed from the electrical coupling between the transparent plate (24) and the circuit portion (55).Type: GrantFiled: March 30, 1999Date of Patent: December 24, 2002Assignee: National Semiconductor CorporationInventors: Ranjan J. Mathew, G. Cade Murray -
Patent number: 6476885Abstract: A liquid crystal display package including a liquid crystal cell having a die with a pixel array, and a transparent plate attached to the die. A liquid crystal material is disposed in a gap region between the die and the transparent plate. The display assembly further includes a containment structure adapted to couple to and at least partially receive liquid crystal cell therein, and an electrical connector portion integrated with the containment structure. A plurality of conductive contacts are positioned in the containment structure for secured support thereof, and in substantially stress-free electrical connection with the pixel array. The conductive contacts further are configured to releasably couple to mating conductive contacts of an opposed electrical connector.Type: GrantFiled: July 19, 1999Date of Patent: November 5, 2002Assignee: National Semiconductor CorporationInventors: G. Cade Murray, Ranjan J. Mathew
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Patent number: 6459143Abstract: Improved methods of packaging external fuses together with integrated circuit devices are described. A pair of frame strips are provided that each have an associated set of contact pads. A resistor paste is applied to one of the contact pad sets and the frame strips are laminated together by curing the resistor paste which is positioned between the contact pad sets. Dice are mounted to the opposite sides of the second contact pads to form integrated circuit devices having integrally packaged external fuses. The packaged devices are eventually singulated for use. In some embodiments, the contact pads each have downturned tabs that form wings on opposite sides of each die. When the dice are flip chips, a device may be attached to a substrate board by soldering both the bumps on the die and the tab wing tips to the substrate board. In a preferred embodiment, the resistor paste is a positive temperature coefficient resistor paste.Type: GrantFiled: April 26, 2001Date of Patent: October 1, 2002Assignee: National Semiconductor CorporationInventors: Inderjit Singh, Hem P. Takiar, Ranjan J. Mathew, Nikhil V. Kelkar
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Patent number: 6384890Abstract: A connection assembly (40) for operably coupling a plurality of independent imaging devices (41, 41′, 41″) to an optical subsystem (42). The connection assembly (40) includes a unitary flex circuit device (43) having an elongated arm portion (45), and a plurality independent finger portions (46, 46′, 46″) extending from a distal end of the arm portion (45). Each finger portion (46, 46′, 46″) defines a coupling region (47, 47′, 47″) adapted to operably couple a respective imaging device (41, 41′, 41″) to a respective finger portion (46, 46′, 46″) for support thereof. The finger portions (46, 46′, 46″) are further adapted to strategically couple each respective imaging device (41, 41′, 41″) to the optical subsystem (42) as a unit. The flex circuit device (30) includes a plurality of circuits (65) terminating at respective terminals (40) of a coupling region (47) thereof.Type: GrantFiled: November 15, 1999Date of Patent: May 7, 2002Assignee: National Semiconductor CorporationInventors: Hem P. Takiar, Ranjan J. Mathew
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Patent number: 6357763Abstract: The present invention provides an improved seal for sealing a liquid crystal display (LCD) device. An improved seal is formed between a transparent plate and a die having a pixel array. The improved seal is configured to encircle the pixel array of the die when the die and the transparent plate are joined. The die and the transparent plate are joined together such that the improved seal is disposed between the transparent plate and the die. In one embodiment, the improved seal is a hybrid seal. The hybrid seal includes a first seal encircling the pixel array of the die and adhesively coupling the transparent plate and the die. The hybrid seal further includes a second seal encircling the second seal. In another embodiment, the first seal lacks a characteristic necessary for an effective seal. The second seal possesses the characteristic, such that the hybrid seal possesses the necessary characteristic.Type: GrantFiled: November 4, 1998Date of Patent: March 19, 2002Assignee: National Semiconductor CorporationInventors: Ranjan J. Mathew, Boonmi Mekdhanasarn
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Patent number: 6356334Abstract: Apparatus are disclosed for Liquid Crystal Display (LCD) assemblies having a display device that is attached to a support substrate. The display device includes a die having a pixel array, and a transparent plate positioned over the die. An adhesive seal couples the die to the transparent plate. The seal together with the transparent plate and the die cooperate to define a sealed volume therebetween encompassing the pixel array. A liquid crystal material is disposed within the sealed volume. A support substrate is coupled to the transparent plate for support of the display device such that the die is substantially insulated from transmission of residual stresses induced by or acting upon the support substrate. Methods of reducing residual stresses in LCD assemblies are also provided.Type: GrantFiled: August 6, 1998Date of Patent: March 12, 2002Assignee: National Semiconductor CorporationInventors: Ranjan J. Mathew, Seshadri Vikram
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Publication number: 20010045712Abstract: The present invention provides an improved seal for sealing a liquid crystal display (LCD) device. An improved seal is formed between a transparent plate and a die having a pixel array. The improved seal is configured to encircle the pixel array of the die when the die and the transparent plate are joined. The die and the transparent plate are joined together such that the improved seal is disposed between the transparent plate and the die. In one embodiment, the improved seal is a hybrid seal. The hybrid seal includes a first seal encircling the pixel array of the die and adhesively coupling the transparent plate and the die. The hybrid seal further includes a second seal encircling the second seal. In another embodiment, the first seal lacks a characteristic necessary for an effective seal. The second seal possesses the characteristic, such that the hybrid seal possesses the necessary characteristic.Type: ApplicationFiled: November 4, 1998Publication date: November 29, 2001Inventors: RANJAN J. MATHEW, BOONMI MEKDHANASARN
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Patent number: 6284566Abstract: An assembly process provides a chip scale package (CSP) which characteristically includes (i) a perforated substrate in which vias can be embedded, (ii) a solder mask on which the integrated circuit die can be attached, and (iii) efficient use of the surface area for electrically routing signals from the integrated circuit die to the external terminals attached to the perforated substrate. The resulting package is highly compact and therefore has a foot print minimally larger than the surface area of the integrated circuit chip. Consequently, the costs of substrate and capsulation materials are minimized. The assembly process allows very high volume production because a large number of integrated circuits can be made on a single unit of the substrate, and singulation is performed in the assembly process at a stage much later than the corresponding stage in a conventional process.Type: GrantFiled: August 31, 1999Date of Patent: September 4, 2001Assignee: National Semiconductor CorporationInventors: Shaw Wei Lee, Hem P. Takiar, Ranjan J. Mathew
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Publication number: 20010015477Abstract: Improved methods of packaging external fuses together with integrated circuit devices are described. A pair of frame strips are provided that each have an associated set of contact pads. A resistor paste is applied to one of the contact pad sets and the frame strips are laminated together by curing the resistor paste which is positioned between the contact pad sets. Dice are mounted to the opposite sides of the second contact pads to form integrated circuit devices having integrally packaged external fuses. The packaged devices are eventually singulated for use. In some embodiments, the contact pads each have downturned tabs that form wings on opposite sides of each die. When the dice are flip chips, a device may be attached to a substrate board by soldering both the bumps on the die and the tab wing tips to the substrate board. In a preferred embodiment, the resistor paste is a positive temperature coefficient resistor paste.Type: ApplicationFiled: April 26, 2001Publication date: August 23, 2001Inventors: Inderjit Singh, Hem P. Takiar, Ranjan J. Mathew, Nikhil V. Kelkar
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Patent number: 6255141Abstract: Improved methods of packaging external fuses together with integrated circuit devices are described. A pair of frame strips are provided that each have an associated set of contact pads. A resistor paste is applied to one of the contact pad sets and the frame strips are laminated together by curing the resistor paste which is positioned between the contact pad sets. Dice are mounted to the opposite sides of the second contact pads to form integrated circuit devices having integrally packaged external fuses. The packaged devices are eventually singulated for use. In some embodiments, the contact pads each have downturned tabs that form wings on opposite sides of each die. When the dice are flip chips, a device may be attached to a substrate board by soldering both the bumps on the die and the tab wing tips to the substrate board. In a preferred embodiment, the resistor paste is a positive temperature coefficient resistor paste.Type: GrantFiled: September 7, 1999Date of Patent: July 3, 2001Assignee: National Semiconductor CorporationInventors: Inderjit Singh, Hem P. Takiar, Ranjan J. Mathew, Nikhil V. Kelkar
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Patent number: 6140708Abstract: An assembly process provides a chip scale package (CSP) which characteristically includes (i) a perforated substrate in which vias can be embedded, (ii) a solder mask on which the integrated circuit die can be attached, and (iii) efficient use of the surface area for electrically routing signals from the integrated circuit die to the external terminals attached to the perforated substrate. The resulting package is highly compact and therefore has a foot print minimally larger than the surface area of the integrated circuit chip. Consequently, the costs of substrate and capsulation materials are minimized. The assembly process allows very high volume production because a large number of integrated circuits can be made on a single unit of the substrate, and singulation is performed in the assembly process at a stage much later than the corresponding stage in a conventional process.Type: GrantFiled: July 8, 1997Date of Patent: October 31, 2000Assignee: National Semiconductor CorporationInventors: Shaw Wei Lee, Hem P. Takiar, Ranjan J. Mathew
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Patent number: 6122033Abstract: The present inventions provide a fusible seal for sealing liquid crystal display (LCD) devices. A fusible seal is formed on a transparent plate or on a die having a pixel array. The fusible seal is configured to encircle the pixel array of the die when the die and the transparent plate are joined. The die and the transparent plate are joined together such that the fusible seal is disposed between the transparent plate and the die. Heat is locally applied to the fusible seal without significantly heating the transparent plate or the die. Heating the fusible seal fuses the transparent plate to the die and encloses the pixel array. A LCD device is thereby formed without the need to cure the entire LCD device, which often times causes warping of the LCD device.Type: GrantFiled: April 6, 1998Date of Patent: September 19, 2000Assignee: National Semiconductor CorporationInventors: Ranjan J. Mathew, Hem P. Takiar
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Patent number: 6054338Abstract: A panel of, for example, bismaleimide triazine (BT) or ceramic (Al.sub.2 O.sub.3) is chosen in size to be substantially filled with and taken up by end-result ball grid array (BGA) devices. The end-result devices are positioned closely together and take up substantially the entire area of the initial panel. Structural weakening is provided at appropriate places in the panel to allow the devices to be readily singulated.Type: GrantFiled: February 20, 1998Date of Patent: April 25, 2000Assignee: National Semiconductor CorporationInventors: Shaw Wei Lee, Hem P. Takiar, Ranjan J. Mathew, Hee Jhin Kim