Abstract: The various embodiments of the present invention provide a low cost, low electrical loss, and low stress panel-based silicon interposer with TPVs. The interposer of the present invention has a thickness of about 100 microns to 200 microns and such thickness is achieved without utilizing a carrier and further wherein no grinding, bonding, or debonding methods are utilized, therefore distinguishing the interposer of the present invention from prior art embodiments.

Abstract: The various embodiments of the present invention provide fine pitch, chip-to-substrate interconnect assemblies, as well as methods of making and using the assemblies. The assemblies generally include a semiconductor having a die pad and a bump disposed thereon and a substrate having a substrate pad disposed thereon. The bump is configured to electrically interconnect at least a portion of the semiconductor with at least a portion of the substrate when the bump is contacted with the substrate pad. In addition, when the bump is contacted to the substrate pad, at least a portion of the bump and at least a portion of the substrate pad are deformed so as to create a non-metallurgical bond therebetween.

Abstract: A 3D interconnect structure comprising an ultra-thin interposer having a plurality of ultra-high density of through-via interconnections defined therein. The 3D interposer electrically connects first and second electronic devices in vertical dimension and has the same or similar through-via density as the first or second electronic devices it connects. The various embodiments of the interconnect structure allows 3D ICs to be stacked with or without TSVs and increases bandwidth between the two electronic devices as compared to other interconnect structures of the prior art. Further, the interconnect structure of the present invention is scalable, testable, thermal manageable, and can be manufactured at relatively low costs. Such a 3D structure can be used for a wide variety of applications that require a variety of heterogeneous ICs, such as logic, memory, graphics, power, wireless and sensors that cannot be integrated into single ICs.

Abstract: A low-temperature process that combines high-aspect-ratio polymer structures with electroless copper plating to create laterally compliant MEMS structures. These structures can be used as IC-package interconnects that can lead to reliable, low-cost and high-performance nano wafer-level packaging. High-aspect-ratio low CTE polyimide structures with low stress, high toughness and strength were fabricated using plasma etching. The dry etching process was tuned to yield a wall angle above 80 degrees leading to an aspect ratio higher than 4. The etching process also leads to roughened sidewalls for selective electroless plating on the sidewalls of the polymer structures. These fabricated structures show reduction in the stresses at the interfaces and superior reliability as IC-package nano interconnects. Metal-coated polymer structures from MEMS fabrication techniques can provide low-cost high-performance solutions for wafer-level-packaging. Other embodiments are also claimed and described.

Abstract: Nano-structured interconnect formation and a reworkable bonding process using solder films. Large area fabrication of nano-structured interconnects is demonstrated at a very fine pitch. This technology can be used for pushing the limits of current flip chip bonding in terms of pitch, number of I/Os, superior combination of electrical and mechanical properties as well as reworkability. Sol-gel and electroless processes were developed to demonstrate film bonding interfaces between metallic pads and nano interconnects. Solution-derived nano-solder technology is an attractive low-cost method for several applications such as MEMS hermetic packaging, compliant interconnect bonding and bump-less nano-interconnects.

Abstract: A low-temperature process that combines high-aspect-ratio polymer structures with electroless copper plating to create laterally compliant MEMS structures. These structures can be used as IC-package interconnects that can lead to reliable, low-cost and high-performance nano wafer-level packaging. High-aspect-ratio low CTE polyimide structures with low stress, high toughness and strength were fabricated using plasma etching. The dry etching process was tuned to yield a wall angle above 80 degrees leading to an aspect ratio higher than 4. The etching process also leads to roughened sidewalls for selective electroless plating on the sidewalls of the polymer structures. These fabricated structures show reduction in the stresses at the interfaces and superior reliability as IC-package nano interconnects. Metal-coated polymer structures from MEMS fabrication techniques can provide low-cost high-performance solutions for wafer-level-packaging. Other embodiments are also claimed and described.

Abstract: A low-temperature process that combines high-aspect-ratio polymer structures with electroless copper plating to create laterally compliant MEMS structures. These structures can be used as IC-package interconnects that can lead to reliable, low-cost and high-performance nano wafer-level packaging. High-aspect-ratio low CTE polyimide structures with low stress, high toughness and strength were fabricated using plasma etching. The dry etching process was tuned to yield a wall angle above 80 degrees leading to an aspect ratio higher than 4. The etching process also leads to roughened sidewalls for selective electroless plating on the sidewalls of the polymer structures. These fabricated structures show reduction in the stresses at the interfaces and superior reliability as IC-package nano interconnects. Metal-coated polymer structures from MEMS fabrication techniques can provide low-cost high-performance solutions for wafer-level-packaging.

Abstract: Generally, the present invention can be viewed as providing a method for manufacturing a multilayer wiring substrate. Briefly described, the method can be broadly conceptualized by the following steps: forming a first conductive connection on a first insulating layer; forming a conductive post on the first conductive connection; forming a second insulating layer on the first conductive connection, the first insulating layer, and the conductive post; exposing the conductive post by removing a portion of the second insulating layer; and forming a second conductive connection on the second insulating layer such that the second conductive connection is electrically connected to the first conductive connection via the conductive post. The second insulating layer can be formed via dry film lamination. In addition, the conductive posts can be exposed by either forming holes in the second insulating layer or by roughening the surface of the second insulating layer.

Abstract: A sintering process is described using a glass-ceramic slurry containing an alloy powder or flakes selected from a group of alloys consisting of:______________________________________ Fe--Cr Cu--Ti Fe--Cr--Ni Ag--Ti Cr--Al Nb--Al Ni--Cr Cu--Al Ni--Al Cu--Al--Cr Fe--Al ______________________________________The slurry is molded and later is sintered in a steam atmosphere at a temperature of about 1000.degree. C. to yield a glass-ceramic substrate toughened against crack propagation and useful in the packaging of semi-conductor device chips.

Abstract: Disclosed is a ceramic substrate having a protective coating on at least one surface thereof which includes:a ceramic substrate having at least one electrically conductive via extending to a surface of the substrate;an electrically conductive I/O pad electrically connected to at least one of the vias;an I/O pin brazed to the I/O pad, the brazed pin having a braze fillet; anda protective layer of polymeric material fully encapsulating the I/O pad, wherein the layer of polymeric material protects the I/O pad from corrosion.

Abstract: A method for fabricating a molecular matrix print head for use in nonimpact electrolytic printers. Green ceramic sheets are stacked and laminated, then embossed with insulators and screened with ruthenium dioxide. The assembly is then co-sintered at less than 1000.degree. C. and the resulting structure smoothed by lapping and finished in a convention fashion.

Abstract: Sintered glass-ceramic substrates containing multi-level, interconnected thick-film circuit patterns of highly conductive metals such as gold, silver or copper are provided which can be fired in air (for gold and silver) or in neutral atmospheres (for copper) at temperatures below the melting points of these metals. This has been made possible by the discovery that finely divided powders of certain glasses described herein sinter to essentially zero porosity at temperatures below 1000.degree. C. while simultaneously maturing to glass-ceramics of low dielectric constant, high flexural strength and low thermal expansivity.

Abstract: Sintered glass-ceramic substrates containing multi-level, interconnected thick-film circuit patterns of highly conductive metals such as gold, silver or copper are provided which can be fired in air (for gold and silver) or in neutral atmospheres (for copper) at temperatures below the melting points of these metals. This has been made possible by the discovery that finely divided powders of certain glasses described herein sinter to essentially zero porosity at temperatures below 1000.degree. C. while simultaneously maturing to glass-ceramics of low dielectric constant, high flexural strength and low thermal expansivity.

Abstract: The formation of sintered glass-ceramic substrates containing multi-level, interconnected thick-film circuit patterns of copper-based conductors obtained by firing in a controlled ambient of hydrogen and H.sub.2 O at temperatures below the melting point of copper.

Abstract: A seal glass for unitizing an array of glass nozzles of an ink jet printer. The seal glasses are corrosion resistant to alkaline and acidic inks, and have low softening points, medium high expansivities and anneal points and are compatible with the nozzle glasses.

Abstract: A method for fabricating an interconnection package for a plurality of semiconductor chips which include the fabrication of a multi-layered glass-ceramic superstructure with a multi-layered distribution of conductors on a preformed multi-layered glass-ceramic base, by the repeatable steps of depositing a conductor pattern on the base and forming thereon a crystallizable glass dielectric layer which is then crystallized to a glass-ceramic prior to further additions of conductor patterns and crystallizable glass layers to form a monolithic compatible substrate all through. Semiconductor chips can be electrically connected to expose conductor patterns at the top surface of the resultant glass-ceramic package.

Abstract: The lifetime of multiple capillary nozzle assemblies embedded in a glass mass, of a multiple nozzle ink-jet printer, can be increased and the thermal and mechanical compatibility of the resulting package enhanced by fabrication of the nozzles from glass compositions comprised of SiO.sub.2, ZrO.sub.2, Na.sub.2 O, K.sub.2 O and MgO. Inclusion of ZrO.sub.2 as well as minor amounts of BaO, MgO, CaO, and Al.sub.2 O.sub.3 enhances the alkali resistance of the glass nozzles. Also, the high SiO.sub.2 content of the glasses combined with the presence of ZrO.sub.2, MgO, CaO, and Al.sub.2 O.sub.3 imparts an acid resistance to the nozzles.

Abstract: A copper oxide containing seal glass is formed by a controlled low temperature process which reduces the formation of seeds in the glass. In one embodiment the glass is prepared in two portions with the first portion containing the high melting oxides and the second portion containing the low melting oxides. The copper oxide is added to the second portion and the two portions are combined to form the seal glass at temperatures below about 800.degree.C which reduces the formation of Cu.sub.2 O crystals in the glass.