Patents by Inventor RASEONG KIM
RASEONG KIM has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240113212Abstract: Technologies for a field effect transistor (FET) with a ferroelectric gate dielectric are disclosed. In an illustrative embodiment, a perovskite stack is grown on a buffer layer as part of manufacturing a transistor. The perovskite stack includes one or more doped semiconductor layers alternating with other lattice-matched layers, such as undoped semiconductor layers. Growing the doped semiconductor layers on lattice-matched layers can improve the quality of the doped semiconductor layers. The lattice-matched layers can be preferentially etched away, leaving the doped semiconductor layers as fins for a ribbon FET. In another embodiment, an interlayer can be deposited on top of a semiconductor layer, and a ferroelectric layer can be deposited on the interlayer. The interlayer can bridge a gap in lattice parameters between the semiconductor layer and the ferroelectric layer.Type: ApplicationFiled: September 29, 2022Publication date: April 4, 2024Applicant: Intel CorporationInventors: Ian Alexander Young, Dmitri Evgenievich Nikonov, Marko Radosavljevic, Matthew V. Metz, John J. Plombon, Raseong Kim, Kevin P. O'Brien, Scott B. Clendenning, Tristan A. Tronic, Dominique A. Adams, Carly Rogan, Hai Li, Arnab Sen Gupta, Gauri Auluck, I-Cheng Tung, Brandon Holybee, Rachel A. Steinhardt, Punyashloka Debashis
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Publication number: 20240113220Abstract: Technologies for a transistor with a thin-film ferroelectric gate dielectric are disclosed. In the illustrative embodiment, a transistor has a thin layer of scandium aluminum nitride (ScxAl1-xN) ferroelectric gate dielectric. The channel of the transistor may be, e.g., gallium nitride or molybdenum disulfide. In one embodiment, the ferroelectric polarization changes when voltage is applied and removed from a gate electrode, facilitating switching of the transistor at a lower applied voltage. In another embodiment, the ferroelectric polarization of a gate dielectric of a transistor changes when the voltage is past a positive threshold value or a negative threshold value. Such a transistor can be used as a one-transistor memory cell.Type: ApplicationFiled: September 30, 2022Publication date: April 4, 2024Applicant: Intel CorporationInventors: Arnab Sen Gupta, Ian Alexander Young, Dmitri Evgenievich Nikonov, Marko Radosavljevic, Matthew V. Metz, John J. Plombon, Raseong Kim, Uygar E. Avci, Kevin P. O'Brien, Scott B. Clendenning, Jason C. Retasket, Shriram Shivaraman, Dominique A. Adams, Carly Rogan, Punyashloka Debashis, Brandon Holybee, Rachel A. Steinhardt, Sudarat Lee
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Publication number: 20240105810Abstract: In one embodiment, transistor device includes a first source or drain material on a substrate, a semiconductor material on the first source or drain material, a second source or drain material on the semiconductor material, a dielectric layer on the substrate and adjacent the first source or drain material, a ferroelectric (FE) material on the dielectric layer and adjacent the semiconductor material, and a gate material on or adjacent to the FE material. The FE material may be a perovskite material and may have a lattice parameter that is less than a lattice parameter of the semiconductor material.Type: ApplicationFiled: September 23, 2022Publication date: March 28, 2024Applicant: Intel CorporationInventors: Rachel A. Steinhardt, Ian Alexander Young, Dmitri Evgenievich Nikonov, Marko Radosavljevic, Matthew V. Metz, John J. Plombon, Raseong Kim, Kevin P. O'Brien, Scott B. Clendenning, Tristan A. Tronic, Dominique A. Adams, Carly Rogan, Arnab Sen Gupta, Brandon Holybee, Punyashloka Debashis, I-Cheng Tung, Gauri Auluck
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Publication number: 20240097031Abstract: In one embodiment, a transistor device includes a gate material layer on a substrate, a ferroelectric (FE) material layer on the gate material, a semiconductor channel material layer on the FE material layer, a first source/drain material on the FE material layer and adjacent the semiconductor channel material layer, and a second source/drain material on the FE material layer and adjacent the semiconductor channel material layer and on an opposite side of the semiconductor channel material layer from the first source/drain material. A first portion of the FE material layer is directly between the gate material and the first source/drain material, and a second portion of the FE material layer is directly between the gate material and the second source/drain material.Type: ApplicationFiled: September 16, 2022Publication date: March 21, 2024Applicant: Intel CorporationInventors: Punyashloka Debashis, Rachel A. Steinhardt, Brandon Holybee, Kevin P. O'Brien, Dmitri Evgenievich Nikonov, John J. Plombon, Ian Alexander Young, Raseong Kim, Carly Rogan, Dominique A. Adams, Arnab Sen Gupta, Marko Radosavljevic, Scott B. Clendenning, Gauri Auluck, Hai Li, Matthew V. Metz, Tristan A. Tronic, I-Cheng Tung
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Publication number: 20230352584Abstract: Technologies for a transistor with a ferroelectric gate dielectric are disclosed. In the illustrative embodiment, a transistor has a ferroelectric gate dielectric that is lattice matched to the channel of the transistor. In one embodiment, the ferroelectric polarization changes when voltage is applied and removed from a gate electrode, facilitating switching of the transistor at a lower applied voltage. In another embodiment, the ferroelectric polarization of a gate dielectric of a transistor changes when the voltage is past a positive threshold value or a negative threshold value. Such a transistor can be used as a one transistor memory cell.Type: ApplicationFiled: May 2, 2022Publication date: November 2, 2023Inventors: Dmitri Evgenievich Nikonov, Chia-Ching Lin, Uygar E. Avci, Tanay A. Gosavi, Raseong Kim, Ian Alexander Young, Hai Li, Ashish Verma Penumatcha, Ramamoorthy Ramesh, Darrell G. Schlom
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Publication number: 20230317847Abstract: Technologies for majority gates are disclosed. In one embodiment, a ferroelectric layer has three inputs and an output adjacent a surface of the ferroelectric. When a voltage is applied to each input, the inputs and a ground plane below the ferroelectric layer form a capacitor. The ferroelectric layer becomes polarized based on the applied voltages at the inputs. The portion of the ferroelectric layer near the output becomes polarized in the direction of polarization of the majority of the inputs. The output voltage then reflects the majority voltage of the inputs.Type: ApplicationFiled: April 1, 2022Publication date: October 5, 2023Applicant: Intel CorporationInventors: Hai Li, Ian Alexander Young, Dmitri Evgenievich Nikonov, Julien Sebot, Raseong Kim, Chia-Ching Lin, Punyashloka Debashis
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Publication number: 20230253475Abstract: Describe is a resonator that uses anti-ferroelectric (AFE) materials in the gate of a transistor as a dielectric. The use of AFE increases the strain/stress generated in the gate of the FinFET. Along with the usual capacitive drive, which is boosted with the increased polarization, additional current drive is also achieved from the piezoelectric response generated to due to AFE material. In some embodiments, the acoustic mode of the resonator is isolated using phononic gratings all around the resonator using the metal line above and vias' to body and dummy fins on the side. As such, a Bragg reflector is formed above or below the AFE based transistor. Increased drive signal from the AFE results in larger output signal and larger bandwidth.Type: ApplicationFiled: April 3, 2023Publication date: August 10, 2023Applicant: Intel CorporationInventors: Tanay Gosavi, Chia-Ching Lin, Raseong Kim, Ashish Verma Penumatcha, Uygar Avci, Ian Young
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Publication number: 20230238444Abstract: Describe is a resonator that uses ferroelectric (FE) materials in the gate of a transistor as a dielectric. The use of FE increases the strain/stress generated in the gate of the FinFET. Along with the usual capacitive drive, which is boosted with the increased polarization, FE material expands or contacts depending on the applied electric field on the gate of the transistor. As such, acoustic waves are generated by switching polarization of the FE materials. In some embodiments, the acoustic mode of the resonator is isolated using phononic gratings all around the resonator using the metal line above and vias' to body and dummy fins on the side. As such, a Bragg reflector is formed above the FE based transistor.Type: ApplicationFiled: April 3, 2023Publication date: July 27, 2023Applicant: Intel CorporationInventors: Tanay Gosavi, Chia-ching Lin, Raseong Kim, Ashish Verma Penumatcha, Uygar Avci, Ian Young
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Publication number: 20230155550Abstract: In one embodiment, a piezo-resistive resonator device includes one or more drive transistors with source and drain regions in a first well and a sense transistor with source and drain regions in a second well of opposite polarity than the first well. The gates of the drive and sense transistor are connected to a first direct current (DC) source. The drain region of the sense transistor is connected to a second DC source, and the source and drain regions of the drive transistor are connected to an alternating current (AC) source.Type: ApplicationFiled: November 18, 2021Publication date: May 18, 2023Applicant: Intel CorporationInventors: Gary A. Allen, Tanay A. Gosavi, Raseong Kim, Dmitri Evgenievich Nikonov, Ian Alexander Young
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Patent number: 11646356Abstract: Describe is a resonator that uses anti-ferroelectric (AFE) materials in the gate of a transistor as a dielectric. The use of AFE increases the strain/stress generated in the gate of the FinFET. Along with the usual capacitive drive, which is boosted with the increased polarization, additional current drive is also achieved from the piezoelectric response generated to due to AFE material. In some embodiments, the acoustic mode of the resonator is isolated using phononic gratings all around the resonator using the metal line above and vias' to body and dummy fins on the side. As such, a Bragg reflector is formed above or below the AFE based transistor. Increased drive signal from the AFE results in larger output signal and larger bandwidth.Type: GrantFiled: January 2, 2019Date of Patent: May 9, 2023Assignee: Intel CorporationInventors: Tanay Gosavi, Chia-ching Lin, Raseong Kim, Ashish Verma Penumatcha, Uygar Avci, Ian Young
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Patent number: 11637191Abstract: Describe is a resonator that uses ferroelectric (FE) materials in the gate of a transistor as a dielectric. The use of FE increases the strain/stress generated in the gate of the FinFET. Along with the usual capacitive drive, which is boosted with the increased polarization, FE material expands or contacts depending on the applied electric field on the gate of the transistor. As such, acoustic waves are generated by switching polarization of the FE materials. In some embodiments, the acoustic mode of the resonator is isolated using phononic gratings all around the resonator using the metal line above and vias' to body and dummy fins on the side. As such, a Bragg reflector is formed above the FE based transistor.Type: GrantFiled: January 2, 2019Date of Patent: April 25, 2023Assignee: Intel CorporationInventors: Tanay Gosavi, Chia-ching Lin, Raseong Kim, Ashish Verma Penumatcha, Uygar Avci, Ian Young
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Patent number: 11605624Abstract: Describe is a resonator that uses ferroelectric (FE) material in a capacitive structure. The resonator includes a first plurality of metal lines extending in a first direction; an array of capacitors comprising ferroelectric material; a second plurality of metal lines extending in the first direction, wherein the array of capacitors is coupled between the first and second plurality of metal lines; and a circuitry to switch polarization of at least one capacitor of the array of capacitors. The switching of polarization regenerates acoustic waves. In some embodiments, the acoustic mode of the resonator is isolated using phononic gratings all around the resonator using metal lines above and adjacent to the FE based capacitors.Type: GrantFiled: January 2, 2019Date of Patent: March 14, 2023Assignee: Intel CorporationInventors: Tanay Gosavi, Chia-ching Lin, Raseong Kim, Ashish Verma Penumatcha, Uygar Avci, Ian Young
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Publication number: 20230057992Abstract: Gallium nitride (GaN) integrated circuit technology with resonators is described. In an example, an integrated circuit structure includes a layer or substrate including gallium and nitrogen. A first plurality of electrodes is over the layer or substrate. A resonator layer is on the first plurality of electrodes, the resonator layer including aluminum and nitrogen. A second plurality of electrodes is on the resonator layer. Individual ones of the second plurality of electrodes are vertically over and aligned with corresponding individual ones of the first plurality of electrodes.Type: ApplicationFiled: August 19, 2021Publication date: February 23, 2023Inventors: Tanay GOSAVI, Raseong KIM, Han Wui THEN, Ian A. YOUNG
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Publication number: 20230058938Abstract: A pbit device, in one embodiment, includes a first field-effect transistor (FET) that includes a source region, a drain region, a source electrode on the source region, a drain electrode on the drain region, a channel region between the source and drain regions, a dielectric layer on a surface over the channel region, an electrode layer above the dielectric layer, and a ferroelectric (FE) material layer between the dielectric layer and the electrode layer. The pbit device also includes a second FET comprising a source electrode, a drain electrode, and a gate electrode. The drain electrode of the second FET is connected to the drain electrode of the first FET.Type: ApplicationFiled: August 23, 2021Publication date: February 23, 2023Applicant: Intel CorporationInventors: Punyashloka Debashis, Dmitri Evgenievich Nikonov, Hai Li, Chia-Ching Lin, Raseong Kim, Tanay A. Gosavi, Ashish Verma Penumatcha, Uygar E. Avci, Marko Radosavljevic, Ian Alexander Young
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Publication number: 20200212532Abstract: Describe is a resonator that uses ferroelectric (FE) material in a capacitive structure. The resonator includes a first plurality of metal lines extending in a first direction; an array of capacitors comprising ferroelectric material; a second plurality of metal lines extending in the first direction, wherein the array of capacitors is coupled between the first and second plurality of metal lines; and a circuitry to switch polarization of at least one capacitor of the array of capacitors. The switching of polarization regenerates acoustic waves. In some embodiments, the acoustic mode of the resonator is isolated using phononic gratings all around the resonator using metal lines above and adjacent to the FE based capacitors.Type: ApplicationFiled: January 2, 2019Publication date: July 2, 2020Applicant: Intel CorporationInventors: Tanay Gosavi, Chia-ching Lin, Raseong Kim, Ashish Verma Penumatcha, Uygar Avci, Ian Young
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Publication number: 20200212193Abstract: Describe is a resonator that uses anti-ferroelectric (AFE) materials in the gate of a transistor as a dielectric. The use of AFE increases the strain/stress generated in the gate of the FinFET. Along with the usual capacitive drive, which is boosted with the increased polarization, additional current drive is also achieved from the piezoelectric response generated to due to AFE material. In some embodiments, the acoustic mode of the resonator is isolated using phononic gratings all around the resonator using the metal line above and vias' to body and dummy fins on the side. As such, a Bragg reflector is formed above or below the AFE based transistor. Increased drive signal from the AFE results in larger output signal and larger bandwidth.Type: ApplicationFiled: January 2, 2019Publication date: July 2, 2020Applicant: Intel Corporation Santa ClaraInventors: Tanay Gosavi, Chia-ching Lin, Raseong Kim, Ashish Verma Penumatcha, Uygar Avci, Ian Young
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Publication number: 20200212194Abstract: Describe is a resonator that uses ferroelectric (FE) materials in the gate of a transistor as a dielectric. The use of FE increases the strain/stress generated in the gate of the FinFET. Along with the usual capacitive drive, which is boosted with the increased polarization, FE material expands or contacts depending on the applied electric field on the gate of the transistor. As such, acoustic waves are generated by switching polarization of the FE materials. In some embodiments, the acoustic mode of the resonator is isolated using phononic gratings all around the resonator using the metal line above and vias' to body and dummy fins on the side. As such, a Bragg reflector is formed above the FE based transistor.Type: ApplicationFiled: January 2, 2019Publication date: July 2, 2020Applicant: Intel CorporationInventors: Tanay Gosavi, Chia-ching Lin, Raseong Kim, Ashish Verma Penumatcha, Uygar Avci, Ian Young
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Publication number: 20200162024Abstract: Embodiments may relate to a piezoresistive oscillator. The oscillator may include a fin field-effect transistor (FinFET) with a source electrode, a drain electrode, and a gate electrode. The oscillator may further include an electrical coupling coupled with the FinFET, wherein the electrical coupling electrically couples the gate electrode to the source electrode or the drain electrode. Other embodiments may be described or claimed.Type: ApplicationFiled: November 16, 2018Publication date: May 21, 2020Applicant: Intel CorporationInventors: Dmitri E. Nikonov, Raseong Kim, Sasikanth Manipatruni, Ian A. Young, Gary Alfred Allen, Tanay Gosavi
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Patent number: 10522683Abstract: An embodiment includes an apparatus comprising: a transistor including an epitaxial source, a channel, and an epitaxial drain; a fin that includes the channel, the channel including a long axis and a short axis; a source contact corresponding to the source; and a drain contact corresponding to the drain; wherein (a) an additional axis intersects each of the source contact, the source, the drain, and the drain contact, and (b) the additional axis is parallel to the long axis. Other embodiments are described herein.Type: GrantFiled: April 25, 2018Date of Patent: December 31, 2019Assignee: Intel CorporationInventors: Raseong Kim, Uygar Avci, Ian Young
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Publication number: 20190334026Abstract: An embodiment includes an apparatus comprising: a transistor including an epitaxial source, a channel, and an epitaxial drain; a fin that includes the channel, the channel including a long axis and a short axis; a source contact corresponding to the source; and a drain contact corresponding to the drain; wherein (a) an additional axis intersects each of the source contact, the source, the drain, and the drain contact, and (b) the additional axis is parallel to the long axis. Other embodiments are described herein.Type: ApplicationFiled: April 25, 2018Publication date: October 31, 2019Inventors: Raseong Kim, Uygar Avci, Ian Young