Patents by Inventor RASEONG KIM

RASEONG KIM has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200212193
    Abstract: Describe is a resonator that uses anti-ferroelectric (AFE) materials in the gate of a transistor as a dielectric. The use of AFE increases the strain/stress generated in the gate of the FinFET. Along with the usual capacitive drive, which is boosted with the increased polarization, additional current drive is also achieved from the piezoelectric response generated to due to AFE material. In some embodiments, the acoustic mode of the resonator is isolated using phononic gratings all around the resonator using the metal line above and vias' to body and dummy fins on the side. As such, a Bragg reflector is formed above or below the AFE based transistor. Increased drive signal from the AFE results in larger output signal and larger bandwidth.
    Type: Application
    Filed: January 2, 2019
    Publication date: July 2, 2020
    Applicant: Intel Corporation Santa Clara
    Inventors: Tanay Gosavi, Chia-ching Lin, Raseong Kim, Ashish Verma Penumatcha, Uygar Avci, Ian Young
  • Publication number: 20200212194
    Abstract: Describe is a resonator that uses ferroelectric (FE) materials in the gate of a transistor as a dielectric. The use of FE increases the strain/stress generated in the gate of the FinFET. Along with the usual capacitive drive, which is boosted with the increased polarization, FE material expands or contacts depending on the applied electric field on the gate of the transistor. As such, acoustic waves are generated by switching polarization of the FE materials. In some embodiments, the acoustic mode of the resonator is isolated using phononic gratings all around the resonator using the metal line above and vias' to body and dummy fins on the side. As such, a Bragg reflector is formed above the FE based transistor.
    Type: Application
    Filed: January 2, 2019
    Publication date: July 2, 2020
    Applicant: Intel Corporation
    Inventors: Tanay Gosavi, Chia-ching Lin, Raseong Kim, Ashish Verma Penumatcha, Uygar Avci, Ian Young
  • Publication number: 20200212532
    Abstract: Describe is a resonator that uses ferroelectric (FE) material in a capacitive structure. The resonator includes a first plurality of metal lines extending in a first direction; an array of capacitors comprising ferroelectric material; a second plurality of metal lines extending in the first direction, wherein the array of capacitors is coupled between the first and second plurality of metal lines; and a circuitry to switch polarization of at least one capacitor of the array of capacitors. The switching of polarization regenerates acoustic waves. In some embodiments, the acoustic mode of the resonator is isolated using phononic gratings all around the resonator using metal lines above and adjacent to the FE based capacitors.
    Type: Application
    Filed: January 2, 2019
    Publication date: July 2, 2020
    Applicant: Intel Corporation
    Inventors: Tanay Gosavi, Chia-ching Lin, Raseong Kim, Ashish Verma Penumatcha, Uygar Avci, Ian Young
  • Publication number: 20200162024
    Abstract: Embodiments may relate to a piezoresistive oscillator. The oscillator may include a fin field-effect transistor (FinFET) with a source electrode, a drain electrode, and a gate electrode. The oscillator may further include an electrical coupling coupled with the FinFET, wherein the electrical coupling electrically couples the gate electrode to the source electrode or the drain electrode. Other embodiments may be described or claimed.
    Type: Application
    Filed: November 16, 2018
    Publication date: May 21, 2020
    Applicant: Intel Corporation
    Inventors: Dmitri E. Nikonov, Raseong Kim, Sasikanth Manipatruni, Ian A. Young, Gary Alfred Allen, Tanay Gosavi
  • Patent number: 10522683
    Abstract: An embodiment includes an apparatus comprising: a transistor including an epitaxial source, a channel, and an epitaxial drain; a fin that includes the channel, the channel including a long axis and a short axis; a source contact corresponding to the source; and a drain contact corresponding to the drain; wherein (a) an additional axis intersects each of the source contact, the source, the drain, and the drain contact, and (b) the additional axis is parallel to the long axis. Other embodiments are described herein.
    Type: Grant
    Filed: April 25, 2018
    Date of Patent: December 31, 2019
    Assignee: Intel Corporation
    Inventors: Raseong Kim, Uygar Avci, Ian Young
  • Publication number: 20190334026
    Abstract: An embodiment includes an apparatus comprising: a transistor including an epitaxial source, a channel, and an epitaxial drain; a fin that includes the channel, the channel including a long axis and a short axis; a source contact corresponding to the source; and a drain contact corresponding to the drain; wherein (a) an additional axis intersects each of the source contact, the source, the drain, and the drain contact, and (b) the additional axis is parallel to the long axis. Other embodiments are described herein.
    Type: Application
    Filed: April 25, 2018
    Publication date: October 31, 2019
    Inventors: Raseong Kim, Uygar Avci, Ian Young
  • Patent number: 10457548
    Abstract: A conductive layer is deposited into a trench in a sacrificial layer on a substrate. An etch stop layer is deposited over the conductive layer. The sacrificial layer is removed to form a gap. In one embodiment, a beam is over a substrate. An interconnect is on the beam. An etch stop layer is over the beam. A gap is between the beam and the etch stop layer.
    Type: Grant
    Filed: June 22, 2015
    Date of Patent: October 29, 2019
    Assignee: Intel Corporation
    Inventors: Kevin Lai Lin, Chytra Pawashe, Raseong Kim, Ian A. Young, Kanwal Jit Singh, Robert L. Bristol
  • Patent number: 10263036
    Abstract: Described is an apparatus which comprises: a magnetic tunneling junction (MTJ) having a free magnetic layer; a piezoelectric layer; and a conducting strain transfer layer coupled to the free magnetic layer and the piezoelectric layer. Described is a method, which comprises: exciting a piezoelectric layer with a voltage driven capacitive stimulus; and writing to a MTJ coupled to the piezoelectric layer via a strain assist layer. Described is also an apparatus which comprises: a transistor; a conductive strain transfer layer coupled to the transistor; and a MTJ device having a free magnetic layer coupled to the conductive strain transfer layer.
    Type: Grant
    Filed: September 25, 2014
    Date of Patent: April 16, 2019
    Assignee: Intel Corporation
    Inventors: Sasikanth Manipatruni, Dmitri E. Nikonov, Asif Khan, Raseong Kim, Tahir Ghani, Ian A. Young
  • Publication number: 20190081044
    Abstract: Embodiments of the present disclosure describe a semiconductor device having sub regions or distances to define threshold voltages. A first semiconductor device includes a first gate stack having a first edge opposing a second edge and a first source region disposed on the semiconductor substrate. A second semiconductor device includes a second gate stack having a third edge opposing a fourth edge and a second source region disposed on the semiconductor substrate. A first distance extends from the first source region to the first edge of the first gate stack and a second distance different from the first distance extends from the second source region to the third edge of the second gate stack.
    Type: Application
    Filed: April 1, 2016
    Publication date: March 14, 2019
    Inventors: Uygar E. AVCI, Raseong KIM, Ian A. YOUNG
  • Patent number: 9947805
    Abstract: Nanowire-based mechanical switching devices are described. For example, a nanowire relay includes a nanowire disposed in a void disposed above a substrate. The nanowire has an anchored portion and a suspended portion. A first gate electrode is disposed adjacent the void, and is spaced apart from the nanowire. A first conductive region is disposed adjacent the first gate electrode and adjacent the void, and is spaced apart from the nanowire.
    Type: Grant
    Filed: May 10, 2016
    Date of Patent: April 17, 2018
    Assignee: Intel Corporation
    Inventors: Chytra Pawashe, Kevin Lin, Anurag Chaudhry, Raseong Kim, Seiyon Kim, Kelin Kuhn, Sasikanth Manipatruni, Rafael Rios, Ian A. Young
  • Publication number: 20180086627
    Abstract: A conductive layer is deposited into a trench in a sacrificial layer on a substrate. An etch stop layer is deposited over the conductive layer. The sacrificial layer is removed to form a gap. In one embodiment, a beam is over a substrate. An interconnect is on the beam. An etch stop layer is over the beam. A gap is between the beam and the etch stop layer.
    Type: Application
    Filed: June 22, 2015
    Publication date: March 29, 2018
    Inventors: Kevin LAI LIN, Chytra PAWASHE, Raseong KIM, Ian A. YOUNG, Kanwal Jit SINGH, Robert L. BRISTOL
  • Publication number: 20170345896
    Abstract: Field effect transistor structures are described that are formed using germanium nanowires. In one example, the structure has a germanium nanowire formed on a substrate along a predetermined confinement orientation, a first doped region of the nanowire at a first end of the nanowire to define a source, a second doped region of the nanowire at a second end of the nanowire to define a drain, and a gate dielectric formed over the nanowire between the source and the drain.
    Type: Application
    Filed: December 24, 2014
    Publication date: November 30, 2017
    Inventors: RASEONG KIM, UYGAR AVCI, IAN YOUNG
  • Publication number: 20170287979
    Abstract: Described is an apparatus which comprises: a magnetic tunneling junction (MTJ) having a free magnetic layer; a piezoelectric layer; and a conducting strain transfer layer coupled to the free magnetic layer and the piezoelectric layer. Described is a method, which comprises: exciting a piezoelectric layer with a voltage driven capacitive stimulus; and writing to a MTJ coupled to the piezoelectric layer via a strain assist layer. Described is also an apparatus which comprises: a transistor; a conductive strain transfer layer coupled to the transistor; and a MTJ device having a free magnetic layer coupled to the conductive strain transfer layer.
    Type: Application
    Filed: September 25, 2014
    Publication date: October 5, 2017
    Inventors: Sasikanth Manipatruni, Dmitri E. Nikonov, Asif Khan, Raseong KIM, Tahir Ghani, Ian A. Young
  • Patent number: 9577060
    Abstract: An embodiment includes a first nonplanar transistor including a first fin that includes first source and drain nodes, and a first channel between the first source and drain nodes; a second nonplanar transistor including a second fin that includes second source and drain nodes, and a second channel between the second source and drain nodes; a nonplanar gate on the first fin between the first source and drain nodes and on the second fin between the second source and drain nodes; and first insulation included between the gate and the first fin and second insulation between the gate and the second fin; wherein the gate mechanically resonates at a first frequency when at least one of the gate and the first fin is actuated with alternating current (AC) to produce periodic forces on the gate. Other embodiments are described herein.
    Type: Grant
    Filed: June 29, 2013
    Date of Patent: February 21, 2017
    Assignee: INTEL CORPORATION
    Inventors: Raseong Kim, Ian A. Young
  • Publication number: 20160329438
    Abstract: Nanowire-based mechanical switching devices are described. For example, a nanowire relay includes a nanowire disposed in a void disposed above a substrate. The nanowire has an anchored portion and a suspended portion. A first gate electrode is disposed adjacent the void, and is spaced apart from the nanowire. A first conductive region is disposed adjacent the first gate electrode and adjacent the void, and is spaced apart from the nanowire.
    Type: Application
    Filed: May 10, 2016
    Publication date: November 10, 2016
    Inventors: Chytra Pawashe, Kevin Lin, Anurag Chaudhry, Raseong Kim, Seiyon Kim, Kelin Kuhn, Sasikanth Manipatruni, Rafael Rios, Ian A. Young
  • Patent number: 9374162
    Abstract: Described herein are technologies related to a semiconductor package that is installed in a portable device for data communications. More particularly, the semiconductor package that contains a memory, a digital logic chip, and an optical port in a single module or mold is described.
    Type: Grant
    Filed: December 19, 2012
    Date of Patent: June 21, 2016
    Assignee: Intel Corporation
    Inventors: Robert L. Sankman, Johanna M. Swan, Dmitri E. Nikonov, Raseong Kim
  • Patent number: 9362074
    Abstract: Nanowire-based mechanical switching devices are described. For example, a nanowire relay includes a nanowire disposed in a void disposed above a substrate. The nanowire has an anchored portion and a suspended portion. A first gate electrode is disposed adjacent the void, and is spaced apart from the nanowire. A first conductive region is disposed adjacent the first gate electrode and adjacent the void, and is spaced apart from the nanowire.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: June 7, 2016
    Assignee: Intel Corporation
    Inventors: Chytra Pawashe, Kevin Lin, Anurag Chaudhry, Raseong Kim, Seiyon Kim, Kelin Kuhn, Sasikanth Manipatruni, Rafael Rios, Ian A. Young
  • Patent number: 9294035
    Abstract: An embodiment includes an oscillator comprising an amplifier formed on a substrate; a multiple gate resonant channel array, formed on the substrate, including: (a) transistors including fins, each of the fins having a channel between source and drain nodes, coupled to common source and drain contacts; and (b) common first and second tri-gates coupled to each of the fins and located between the source and drain contacts; wherein the fins mechanically resonate at a first frequency when one of the first and second tri-gates is periodically activated to produce periodic downward forces on the fins. Other embodiments include a non planar transistor with a channel between the source and drain nodes and a tri-gate on the fin; wherein the fin mechanically resonates when the first tri-gate is periodically activated to produce periodic downward forces on the fin. Other embodiments are described herein.
    Type: Grant
    Filed: March 28, 2013
    Date of Patent: March 22, 2016
    Assignee: Intel Corporation
    Inventors: Sasikanth Manipatruni, Raseong Kim, Rajashree Baskaran, Rajeev K. Dokania, Ian A. Young
  • Publication number: 20160056252
    Abstract: An embodiment includes a first nonplanar transistor including a first fin that includes first source and drain nodes, and a first channel between the first source and drain nodes; a second nonplanar transistor including a second fin that includes second source and drain nodes, and a second channel between the second source and drain nodes; a nonplanar gate on the first fin between the first source and drain nodes and on the second fin between the second source and drain nodes; and first insulation included between the gate and the first fin and second insulation between the gate and the second fin; wherein the gate mechanically resonates at a first frequency when at least one of the gate and the first fin is actuated with alternating current (AC) to produce periodic forces on the gate. Other embodiments are described herein.
    Type: Application
    Filed: June 29, 2013
    Publication date: February 25, 2016
    Inventors: Raseong Kim, Ian A. Young
  • Publication number: 20160056278
    Abstract: Tunneling field effect transistors (TFETs) with undoped drain underlap wrap-around regions are described. For example, a tunneling field effect transistor (TFET) includes a homojunction active region formed above a substrate. The homojunction active region includes a doped source region, an undoped channel region, a wrapped-around region, and a doped drain region. A gate electrode and gate dielectric layer are formed on the undoped channel region, between the source and wrapped-around regions.
    Type: Application
    Filed: June 27, 2013
    Publication date: February 25, 2016
    Applicant: INTEL CORPORATION
    Inventors: Uygar E. AVCI, Raseong KIM, Ian A. YOUNG