Patents by Inventor RASEONG KIM

RASEONG KIM has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250006840
    Abstract: In one embodiment, a negative capacitance transistor device includes a perovskite semiconductor material layer with first and second perovskite conductors on opposite ends of the perovskite semiconductor material layer. The device further includes a dielectric material layer on the perovskite semiconductor material layer between the first and second perovskite conductors, a perovskite ferroelectric material layer on the dielectric material layer, and a third perovskite conductor on the perovskite ferroelectric material layer.
    Type: Application
    Filed: June 29, 2023
    Publication date: January 2, 2025
    Applicant: INTEL CORPORATION
    Inventors: Rachel A. Steinhardt, Kevin P. O'Brien, Dmitri Evgenievich Nikonov, John J. Plombon, Tristan A. Tronic, Ian Alexander Young, Matthew V. Metz, Marko Radosavljevic, Carly Rogan, Brandon Holybee, Raseong Kim, Punyashloka Debashis, Dominique A. Adams, I-Cheng Tung, Arnab Sen Gupta, Gauri Auluck, Scott B. Clendenning, Pratyush P. Buragohain, Hai Li
  • Publication number: 20250006791
    Abstract: Perovskite oxide field effect transistors comprise perovskite oxide materials for the channel, source, drain, and gate oxide regions. The source and drain regions are doped with a higher concentration of n-type or p-type dopants (depending on whether the transistor is an n-type or p-type transistor) than the dopant concentration in the channel region to minimize Schottky barrier height between the source and drain regions and the source and drain metal contact and contact resistance.
    Type: Application
    Filed: July 1, 2023
    Publication date: January 2, 2025
    Applicant: Intel Corporation
    Inventors: Rachel A. Steinhardt, Kevin P. O'Brien, Dominique A. Adams, Gauri Auluck, Pratyush P. Buragohain, Scott B. Clendenning, Punyashloka Debashis, Arnab Sen Gupta, Brandon Holybee, Raseong Kim, Matthew V. Metz, John J. Plombon, Marko Radosavljevic, Carly Rogan, Tristan A. Tronic, I-Cheng Tung, Ian Alexander Young, Dmitri Evgenievich Nikonov
  • Publication number: 20250008852
    Abstract: A two-terminal ferroelectric perovskite diode comprises a region of ferroelectric perovskite material positioned adjacent to a region of n-type doped perovskite semiconductor material. Asserting a positive voltage across the diode can cause the polarization of the ferroelectric perovskite material to be set in a first direction that causes the diode to be placed in a low resistance state due to the formation of an accumulation region in the perovskite semiconductor material at the ferroelectric perovskite-perovskite semiconductor boundary. Asserting a negative voltage across the diode can cause the polarization of the ferroelectric perovskite material to be set in a second direction that causes the diode to be placed in a high resistance state due to the formation of a depletion region in the perovskite semiconductor material at the ferroelectric perovskite-perovskite semiconductor material. These non-volatile low and high resistance states enable the diode to be used as a non-volatile memory element.
    Type: Application
    Filed: July 1, 2023
    Publication date: January 2, 2025
    Applicant: Intel Corporation
    Inventors: Punyashloka Debashis, Dominique A. Adams, Gauri Auluck, Scott B. Clendenning, Arnab Sen Gupta, Brandon Holybee, Raseong Kim, Matthew V. Metz, Kevin P. O'Brien, John J. Plombon, Marko Radosavljevic, Carly Rogan, Hojoon Ryu, Rachel A. Steinhardt, Tristan A. Tronic, I-Cheng Tung, Ian Alexander Young, Dmitri Evgenievich Nikonov
  • Publication number: 20250006839
    Abstract: A transistor device may include a first perovskite gate material, a first perovskite ferroelectric material on the first gate material, a first p-type perovskite semiconductor material on the first ferroelectric material, a second perovskite ferroelectric material on the first semiconductor material, a second perovskite gate material on the second ferroelectric material, a third perovskite ferroelectric material on the second gate material, a second p-type perovskite semiconductor material on the third ferroelectric material, a fourth perovskite ferroelectric material on the second semiconductor material, a third perovskite gate material on the fourth ferroelectric material, a first source/drain metal adjacent a first side of each of the first semiconductor material and the second semiconductor material, a second source/drain metal adjacent a second side opposite the first side of each of the first semiconductor material and the second semiconductor material, and dielectric materials between the source/drain
    Type: Application
    Filed: June 28, 2023
    Publication date: January 2, 2025
    Applicant: Intel Corporation
    Inventors: Kevin P. O'Brien, Dmitri Evgenievich Nikonov, Rachel A. Steinhardt, Pratyush P. Buragohain, John J. Plombon, Hai Li, Gauri Auluck, I-Cheng Tung, Tristan A. Tronic, Dominique A. Adams, Punyashloka Debashis, Raseong Kim, Carly Rogan, Arnab Sen Gupta, Brandon Holybee, Marko Radosavljevic, Uygar E. Avci, Ian Alexander Young, Matthew V. Metz
  • Publication number: 20250006841
    Abstract: Technologies for a field effect transistor (FET) with a ferroelectric gate dielectric are disclosed. In an illustrative embodiment, a transistor includes a gate of strontium ruthenate and a ferroelectric gate dielectric layer of barium titanate. In order to prevent migration of ruthenium from the strontium ruthenate to the barium titanate, a barrier layer is placed between the gate and the ferroelectric gate dielectric layer. The barrier layer may be a metal oxide, such as strontium oxide, barium oxide, zirconium oxide, etc.
    Type: Application
    Filed: June 30, 2023
    Publication date: January 2, 2025
    Applicant: Intel Corporation
    Inventors: Arnab Sen Gupta, Dmitri Evgenievich Nikonov, John J. Plombon, Rachel A. Steinhardt, Punyashloka Debashis, Kevin P. O'Brien, Matthew V. Metz, Scott B. Clendenning, Brandon Holybee, Marko Radosavljevic, Ian Alexander Young, I-Cheng Tung, Sudarat Lee, Raseong Kim, Pratyush P. Buragohain
  • Publication number: 20240429301
    Abstract: A transistor device may be formed with a doped perovskite material as a channel region. The doped perovskite material may be formed via an epitaxial growth process from a seed layer, and the channel regions of the transistor device may be formed from lateral overgrowth from the epitaxial growth process.
    Type: Application
    Filed: June 26, 2023
    Publication date: December 26, 2024
    Applicant: Intel Corporation
    Inventors: Rachel A. Steinhardt, Dmitri Evgenievich Nikonov, Kevin P. O'Brien, John J. Plombon, Tristan A. Tronic, Ian Alexander Young, Matthew V. Metz, Marko Radosavljevic, Carly Rogan, Brandon Holybee, Raseong Kim, Punyashloka Debashis, Dominique A. Adams, I-Cheng Tung, Arnab Sen Gupta, Gauri Auluck, Scott B. Clendenning, Pratyush P. Buragohain
  • Patent number: 12125893
    Abstract: Describe is a resonator that uses anti-ferroelectric (AFE) materials in the gate of a transistor as a dielectric. The use of AFE increases the strain/stress generated in the gate of the FinFET. Along with the usual capacitive drive, which is boosted with the increased polarization, additional current drive is also achieved from the piezoelectric response generated to due to AFE material. In some embodiments, the acoustic mode of the resonator is isolated using phononic gratings all around the resonator using the metal line above and vias' to body and dummy fins on the side. As such, a Bragg reflector is formed above or below the AFE based transistor. Increased drive signal from the AFE results in larger output signal and larger bandwidth.
    Type: Grant
    Filed: April 3, 2023
    Date of Patent: October 22, 2024
    Assignee: Intel Corporation
    Inventors: Tanay Gosavi, Chia-Ching Lin, Raseong Kim, Ashish Verma Penumatcha, Uygar Avci, Ian Young
  • Patent number: 12113117
    Abstract: Describe is a resonator that uses ferroelectric (FE) materials in the gate of a transistor as a dielectric. The use of FE increases the strain/stress generated in the gate of the FinFET. Along with the usual capacitive drive, which is boosted with the increased polarization, FE material expands or contacts depending on the applied electric field on the gate of the transistor. As such, acoustic waves are generated by switching polarization of the FE materials. In some embodiments, the acoustic mode of the resonator is isolated using phononic gratings all around the resonator using the metal line above and vias' to body and dummy fins on the side. As such, a Bragg reflector is formed above the FE based transistor.
    Type: Grant
    Filed: April 3, 2023
    Date of Patent: October 8, 2024
    Assignee: Intel Corporation
    Inventors: Tanay Gosavi, Chia-ching Lin, Raseong Kim, Ashish Verma Penumatcha, Uygar Avci, Ian Young
  • Publication number: 20240113220
    Abstract: Technologies for a transistor with a thin-film ferroelectric gate dielectric are disclosed. In the illustrative embodiment, a transistor has a thin layer of scandium aluminum nitride (ScxAl1-xN) ferroelectric gate dielectric. The channel of the transistor may be, e.g., gallium nitride or molybdenum disulfide. In one embodiment, the ferroelectric polarization changes when voltage is applied and removed from a gate electrode, facilitating switching of the transistor at a lower applied voltage. In another embodiment, the ferroelectric polarization of a gate dielectric of a transistor changes when the voltage is past a positive threshold value or a negative threshold value. Such a transistor can be used as a one-transistor memory cell.
    Type: Application
    Filed: September 30, 2022
    Publication date: April 4, 2024
    Applicant: Intel Corporation
    Inventors: Arnab Sen Gupta, Ian Alexander Young, Dmitri Evgenievich Nikonov, Marko Radosavljevic, Matthew V. Metz, John J. Plombon, Raseong Kim, Uygar E. Avci, Kevin P. O'Brien, Scott B. Clendenning, Jason C. Retasket, Shriram Shivaraman, Dominique A. Adams, Carly Rogan, Punyashloka Debashis, Brandon Holybee, Rachel A. Steinhardt, Sudarat Lee
  • Publication number: 20240113212
    Abstract: Technologies for a field effect transistor (FET) with a ferroelectric gate dielectric are disclosed. In an illustrative embodiment, a perovskite stack is grown on a buffer layer as part of manufacturing a transistor. The perovskite stack includes one or more doped semiconductor layers alternating with other lattice-matched layers, such as undoped semiconductor layers. Growing the doped semiconductor layers on lattice-matched layers can improve the quality of the doped semiconductor layers. The lattice-matched layers can be preferentially etched away, leaving the doped semiconductor layers as fins for a ribbon FET. In another embodiment, an interlayer can be deposited on top of a semiconductor layer, and a ferroelectric layer can be deposited on the interlayer. The interlayer can bridge a gap in lattice parameters between the semiconductor layer and the ferroelectric layer.
    Type: Application
    Filed: September 29, 2022
    Publication date: April 4, 2024
    Applicant: Intel Corporation
    Inventors: Ian Alexander Young, Dmitri Evgenievich Nikonov, Marko Radosavljevic, Matthew V. Metz, John J. Plombon, Raseong Kim, Kevin P. O'Brien, Scott B. Clendenning, Tristan A. Tronic, Dominique A. Adams, Carly Rogan, Hai Li, Arnab Sen Gupta, Gauri Auluck, I-Cheng Tung, Brandon Holybee, Rachel A. Steinhardt, Punyashloka Debashis
  • Publication number: 20240105810
    Abstract: In one embodiment, transistor device includes a first source or drain material on a substrate, a semiconductor material on the first source or drain material, a second source or drain material on the semiconductor material, a dielectric layer on the substrate and adjacent the first source or drain material, a ferroelectric (FE) material on the dielectric layer and adjacent the semiconductor material, and a gate material on or adjacent to the FE material. The FE material may be a perovskite material and may have a lattice parameter that is less than a lattice parameter of the semiconductor material.
    Type: Application
    Filed: September 23, 2022
    Publication date: March 28, 2024
    Applicant: Intel Corporation
    Inventors: Rachel A. Steinhardt, Ian Alexander Young, Dmitri Evgenievich Nikonov, Marko Radosavljevic, Matthew V. Metz, John J. Plombon, Raseong Kim, Kevin P. O'Brien, Scott B. Clendenning, Tristan A. Tronic, Dominique A. Adams, Carly Rogan, Arnab Sen Gupta, Brandon Holybee, Punyashloka Debashis, I-Cheng Tung, Gauri Auluck
  • Publication number: 20240097031
    Abstract: In one embodiment, a transistor device includes a gate material layer on a substrate, a ferroelectric (FE) material layer on the gate material, a semiconductor channel material layer on the FE material layer, a first source/drain material on the FE material layer and adjacent the semiconductor channel material layer, and a second source/drain material on the FE material layer and adjacent the semiconductor channel material layer and on an opposite side of the semiconductor channel material layer from the first source/drain material. A first portion of the FE material layer is directly between the gate material and the first source/drain material, and a second portion of the FE material layer is directly between the gate material and the second source/drain material.
    Type: Application
    Filed: September 16, 2022
    Publication date: March 21, 2024
    Applicant: Intel Corporation
    Inventors: Punyashloka Debashis, Rachel A. Steinhardt, Brandon Holybee, Kevin P. O'Brien, Dmitri Evgenievich Nikonov, John J. Plombon, Ian Alexander Young, Raseong Kim, Carly Rogan, Dominique A. Adams, Arnab Sen Gupta, Marko Radosavljevic, Scott B. Clendenning, Gauri Auluck, Hai Li, Matthew V. Metz, Tristan A. Tronic, I-Cheng Tung
  • Publication number: 20230352584
    Abstract: Technologies for a transistor with a ferroelectric gate dielectric are disclosed. In the illustrative embodiment, a transistor has a ferroelectric gate dielectric that is lattice matched to the channel of the transistor. In one embodiment, the ferroelectric polarization changes when voltage is applied and removed from a gate electrode, facilitating switching of the transistor at a lower applied voltage. In another embodiment, the ferroelectric polarization of a gate dielectric of a transistor changes when the voltage is past a positive threshold value or a negative threshold value. Such a transistor can be used as a one transistor memory cell.
    Type: Application
    Filed: May 2, 2022
    Publication date: November 2, 2023
    Inventors: Dmitri Evgenievich Nikonov, Chia-Ching Lin, Uygar E. Avci, Tanay A. Gosavi, Raseong Kim, Ian Alexander Young, Hai Li, Ashish Verma Penumatcha, Ramamoorthy Ramesh, Darrell G. Schlom
  • Publication number: 20230317847
    Abstract: Technologies for majority gates are disclosed. In one embodiment, a ferroelectric layer has three inputs and an output adjacent a surface of the ferroelectric. When a voltage is applied to each input, the inputs and a ground plane below the ferroelectric layer form a capacitor. The ferroelectric layer becomes polarized based on the applied voltages at the inputs. The portion of the ferroelectric layer near the output becomes polarized in the direction of polarization of the majority of the inputs. The output voltage then reflects the majority voltage of the inputs.
    Type: Application
    Filed: April 1, 2022
    Publication date: October 5, 2023
    Applicant: Intel Corporation
    Inventors: Hai Li, Ian Alexander Young, Dmitri Evgenievich Nikonov, Julien Sebot, Raseong Kim, Chia-Ching Lin, Punyashloka Debashis
  • Publication number: 20230253475
    Abstract: Describe is a resonator that uses anti-ferroelectric (AFE) materials in the gate of a transistor as a dielectric. The use of AFE increases the strain/stress generated in the gate of the FinFET. Along with the usual capacitive drive, which is boosted with the increased polarization, additional current drive is also achieved from the piezoelectric response generated to due to AFE material. In some embodiments, the acoustic mode of the resonator is isolated using phononic gratings all around the resonator using the metal line above and vias' to body and dummy fins on the side. As such, a Bragg reflector is formed above or below the AFE based transistor. Increased drive signal from the AFE results in larger output signal and larger bandwidth.
    Type: Application
    Filed: April 3, 2023
    Publication date: August 10, 2023
    Applicant: Intel Corporation
    Inventors: Tanay Gosavi, Chia-Ching Lin, Raseong Kim, Ashish Verma Penumatcha, Uygar Avci, Ian Young
  • Publication number: 20230238444
    Abstract: Describe is a resonator that uses ferroelectric (FE) materials in the gate of a transistor as a dielectric. The use of FE increases the strain/stress generated in the gate of the FinFET. Along with the usual capacitive drive, which is boosted with the increased polarization, FE material expands or contacts depending on the applied electric field on the gate of the transistor. As such, acoustic waves are generated by switching polarization of the FE materials. In some embodiments, the acoustic mode of the resonator is isolated using phononic gratings all around the resonator using the metal line above and vias' to body and dummy fins on the side. As such, a Bragg reflector is formed above the FE based transistor.
    Type: Application
    Filed: April 3, 2023
    Publication date: July 27, 2023
    Applicant: Intel Corporation
    Inventors: Tanay Gosavi, Chia-ching Lin, Raseong Kim, Ashish Verma Penumatcha, Uygar Avci, Ian Young
  • Publication number: 20230155550
    Abstract: In one embodiment, a piezo-resistive resonator device includes one or more drive transistors with source and drain regions in a first well and a sense transistor with source and drain regions in a second well of opposite polarity than the first well. The gates of the drive and sense transistor are connected to a first direct current (DC) source. The drain region of the sense transistor is connected to a second DC source, and the source and drain regions of the drive transistor are connected to an alternating current (AC) source.
    Type: Application
    Filed: November 18, 2021
    Publication date: May 18, 2023
    Applicant: Intel Corporation
    Inventors: Gary A. Allen, Tanay A. Gosavi, Raseong Kim, Dmitri Evgenievich Nikonov, Ian Alexander Young
  • Patent number: 11646356
    Abstract: Describe is a resonator that uses anti-ferroelectric (AFE) materials in the gate of a transistor as a dielectric. The use of AFE increases the strain/stress generated in the gate of the FinFET. Along with the usual capacitive drive, which is boosted with the increased polarization, additional current drive is also achieved from the piezoelectric response generated to due to AFE material. In some embodiments, the acoustic mode of the resonator is isolated using phononic gratings all around the resonator using the metal line above and vias' to body and dummy fins on the side. As such, a Bragg reflector is formed above or below the AFE based transistor. Increased drive signal from the AFE results in larger output signal and larger bandwidth.
    Type: Grant
    Filed: January 2, 2019
    Date of Patent: May 9, 2023
    Assignee: Intel Corporation
    Inventors: Tanay Gosavi, Chia-ching Lin, Raseong Kim, Ashish Verma Penumatcha, Uygar Avci, Ian Young
  • Patent number: 11637191
    Abstract: Describe is a resonator that uses ferroelectric (FE) materials in the gate of a transistor as a dielectric. The use of FE increases the strain/stress generated in the gate of the FinFET. Along with the usual capacitive drive, which is boosted with the increased polarization, FE material expands or contacts depending on the applied electric field on the gate of the transistor. As such, acoustic waves are generated by switching polarization of the FE materials. In some embodiments, the acoustic mode of the resonator is isolated using phononic gratings all around the resonator using the metal line above and vias' to body and dummy fins on the side. As such, a Bragg reflector is formed above the FE based transistor.
    Type: Grant
    Filed: January 2, 2019
    Date of Patent: April 25, 2023
    Assignee: Intel Corporation
    Inventors: Tanay Gosavi, Chia-ching Lin, Raseong Kim, Ashish Verma Penumatcha, Uygar Avci, Ian Young
  • Patent number: 11605624
    Abstract: Describe is a resonator that uses ferroelectric (FE) material in a capacitive structure. The resonator includes a first plurality of metal lines extending in a first direction; an array of capacitors comprising ferroelectric material; a second plurality of metal lines extending in the first direction, wherein the array of capacitors is coupled between the first and second plurality of metal lines; and a circuitry to switch polarization of at least one capacitor of the array of capacitors. The switching of polarization regenerates acoustic waves. In some embodiments, the acoustic mode of the resonator is isolated using phononic gratings all around the resonator using metal lines above and adjacent to the FE based capacitors.
    Type: Grant
    Filed: January 2, 2019
    Date of Patent: March 14, 2023
    Assignee: Intel Corporation
    Inventors: Tanay Gosavi, Chia-ching Lin, Raseong Kim, Ashish Verma Penumatcha, Uygar Avci, Ian Young