Abstract: A conductive layer is deposited into a trench in a sacrificial layer on a substrate. An etch stop layer is deposited over the conductive layer. The sacrificial layer is removed to form a gap. In one embodiment, a beam is over a substrate. An interconnect is on the beam. An etch stop layer is over the beam. A gap is between the beam and the etch stop layer.

Abstract: Described is an apparatus which comprises: a magnetic tunneling junction (MTJ) having a free magnetic layer; a piezoelectric layer; and a conducting strain transfer layer coupled to the free magnetic layer and the piezoelectric layer. Described is a method, which comprises: exciting a piezoelectric layer with a voltage driven capacitive stimulus; and writing to a MTJ coupled to the piezoelectric layer via a strain assist layer. Described is also an apparatus which comprises: a transistor; a conductive strain transfer layer coupled to the transistor; and a MTJ device having a free magnetic layer coupled to the conductive strain transfer layer.

Abstract: Embodiments of the present disclosure describe a semiconductor device having sub regions or distances to define threshold voltages. A first semiconductor device includes a first gate stack having a first edge opposing a second edge and a first source region disposed on the semiconductor substrate. A second semiconductor device includes a second gate stack having a third edge opposing a fourth edge and a second source region disposed on the semiconductor substrate. A first distance extends from the first source region to the first edge of the first gate stack and a second distance different from the first distance extends from the second source region to the third edge of the second gate stack.

Abstract: Nanowire-based mechanical switching devices are described. For example, a nanowire relay includes a nanowire disposed in a void disposed above a substrate. The nanowire has an anchored portion and a suspended portion. A first gate electrode is disposed adjacent the void, and is spaced apart from the nanowire. A first conductive region is disposed adjacent the first gate electrode and adjacent the void, and is spaced apart from the nanowire.

Abstract: A conductive layer is deposited into a trench in a sacrificial layer on a substrate. An etch stop layer is deposited over the conductive layer. The sacrificial layer is removed to form a gap. In one embodiment, a beam is over a substrate. An interconnect is on the beam. An etch stop layer is over the beam. A gap is between the beam and the etch stop layer.

Abstract: Field effect transistor structures are described that are formed using germanium nanowires. In one example, the structure has a germanium nanowire formed on a substrate along a predetermined confinement orientation, a first doped region of the nanowire at a first end of the nanowire to define a source, a second doped region of the nanowire at a second end of the nanowire to define a drain, and a gate dielectric formed over the nanowire between the source and the drain.

Abstract: Described is an apparatus which comprises: a magnetic tunneling junction (MTJ) having a free magnetic layer; a piezoelectric layer; and a conducting strain transfer layer coupled to the free magnetic layer and the piezoelectric layer. Described is a method, which comprises: exciting a piezoelectric layer with a voltage driven capacitive stimulus; and writing to a MTJ coupled to the piezoelectric layer via a strain assist layer. Described is also an apparatus which comprises: a transistor; a conductive strain transfer layer coupled to the transistor; and a MTJ device having a free magnetic layer coupled to the conductive strain transfer layer.

Abstract: An embodiment includes a first nonplanar transistor including a first fin that includes first source and drain nodes, and a first channel between the first source and drain nodes; a second nonplanar transistor including a second fin that includes second source and drain nodes, and a second channel between the second source and drain nodes; a nonplanar gate on the first fin between the first source and drain nodes and on the second fin between the second source and drain nodes; and first insulation included between the gate and the first fin and second insulation between the gate and the second fin; wherein the gate mechanically resonates at a first frequency when at least one of the gate and the first fin is actuated with alternating current (AC) to produce periodic forces on the gate. Other embodiments are described herein.

Abstract: Nanowire-based mechanical switching devices are described. For example, a nanowire relay includes a nanowire disposed in a void disposed above a substrate. The nanowire has an anchored portion and a suspended portion. A first gate electrode is disposed adjacent the void, and is spaced apart from the nanowire. A first conductive region is disposed adjacent the first gate electrode and adjacent the void, and is spaced apart from the nanowire.

Abstract: Described herein are technologies related to a semiconductor package that is installed in a portable device for data communications. More particularly, the semiconductor package that contains a memory, a digital logic chip, and an optical port in a single module or mold is described.

Abstract: Nanowire-based mechanical switching devices are described. For example, a nanowire relay includes a nanowire disposed in a void disposed above a substrate. The nanowire has an anchored portion and a suspended portion. A first gate electrode is disposed adjacent the void, and is spaced apart from the nanowire. A first conductive region is disposed adjacent the first gate electrode and adjacent the void, and is spaced apart from the nanowire.

Abstract: An embodiment includes an oscillator comprising an amplifier formed on a substrate; a multiple gate resonant channel array, formed on the substrate, including: (a) transistors including fins, each of the fins having a channel between source and drain nodes, coupled to common source and drain contacts; and (b) common first and second tri-gates coupled to each of the fins and located between the source and drain contacts; wherein the fins mechanically resonate at a first frequency when one of the first and second tri-gates is periodically activated to produce periodic downward forces on the fins. Other embodiments include a non planar transistor with a channel between the source and drain nodes and a tri-gate on the fin; wherein the fin mechanically resonates when the first tri-gate is periodically activated to produce periodic downward forces on the fin. Other embodiments are described herein.

Abstract: An embodiment includes a first nonplanar transistor including a first fin that includes first source and drain nodes, and a first channel between the first source and drain nodes; a second nonplanar transistor including a second fin that includes second source and drain nodes, and a second channel between the second source and drain nodes; a nonplanar gate on the first fin between the first source and drain nodes and on the second fin between the second source and drain nodes; and first insulation included between the gate and the first fin and second insulation between the gate and the second fin; wherein the gate mechanically resonates at a first frequency when at least one of the gate and the first fin is actuated with alternating current (AC) to produce periodic forces on the gate. Other embodiments are described herein.

Abstract: Tunneling field effect transistors (TFETs) with undoped drain underlap wrap-around regions are described. For example, a tunneling field effect transistor (TFET) includes a homojunction active region formed above a substrate. The homojunction active region includes a doped source region, an undoped channel region, a wrapped-around region, and a doped drain region. A gate electrode and gate dielectric layer are formed on the undoped channel region, between the source and wrapped-around regions.

Abstract: Three dimensional integrated circuits including semiconductive organic materials are described. In some embodiments, the three dimensional integrated circuits include one or more electronic components that include a semiconductive region formed of one or more semiconductive organic materials. The electronic components of the three dimensional integrated circuits may also include insulating regions formed from organic insulating materials, and conductive regions form from conductive materials. The three dimensional integrated circuits may be formed by an additive manufacturing process such as three dimensional printing. Apparatus and methods for producing and testing three dimensional integrated circuits are also described.

Abstract: An embodiment includes an oscillator comprising an amplifier formed on a substrate; a multiple gate resonant channel array, formed on the substrate, including: (a) transistors including fins, each of the fins having a channel between source and drain nodes, coupled to common source and drain contacts; and (b) common first and second tri-gates coupled to each of the fins and located between the source and drain contacts; wherein the fins mechanically resonate at a first frequency when one of the first and second tri-gates is periodically activated to produce periodic downward forces on the fins. Other embodiments include a non planar transistor with a channel between the source and drain nodes and a tri-gate on the fin; wherein the fin mechanically resonates when the first tri-gate is periodically activated to produce periodic downward forces on the fin. Other embodiments are described herein.

Abstract: Nanowire-based mechanical switching devices are described. For example, a nanowire relay includes a nanowire disposed in a void disposed above a substrate. The nanowire has an anchored portion and a suspended portion. A first gate electrode is disposed adjacent the void, and is spaced apart from the nanowire. A first conductive region is disposed adjacent the first gate electrode and adjacent the void, and is spaced apart from the nanowire.

Abstract: A method, electronic device and system for displaying background images on an electronic device, wherein the electronic device includes a face that has at least one edge and a display visible in the face. The display extends to at least one edge of the face. Furthermore, a processor is coupled to the display and a photosensor is coupled to the processor. The photosensor is configured to capture background images of a background obscured behind the device when viewing the device face. The processor is configured to composite the background image with a second image.

Abstract: Described herein are technologies related to a semiconductor package that is installed in a portable device for data communications. More particularly, the semiconductor package that contains a memory, a digital logic chip, and an optical port in a single module or mold is described.

Abstract: Three dimensional integrated circuits including semiconductive organic materials are described. In some embodiments, the three dimensional integrated circuits include one or more electronic components that include a semiconductive region formed of one or more semiconductive organic materials. The electronic components of the three dimensional integrated circuits may also include insulating regions formed from organic insulating materials, and conductive regions form from conductive materials. The three dimensional integrated circuits may be formed by an additive manufacturing process such as three dimensional printing. Apparatus and methods for producing and testing three dimensional integrated circuits are also described.