Patents by Inventor Ravi Iyer
Ravi Iyer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20160306965Abstract: Systems and methods are disclosed for associating an entity with a risk score that may indicate a security threat associated with the entity's activity. An exemplary method may involve monitoring the activity of a subset of the set of entities (e.g., entities included in a watch list) by executing a search query against events indicating the activity of the subset of entities. The events may be associated with timestamps and may include machine data. Executing the search query may produce search results that pertain to activity of a particular entity from the subset. The search results may be evaluated based on a triggering condition corresponding to the statistical baseline. When the triggering condition is met, a risk score for the particular entity may be updated. The updated risk score may be displayed to a user via a graphical user interface (GUI).Type: ApplicationFiled: April 20, 2015Publication date: October 20, 2016Inventors: Ravi Iyer, Devendra Badhani, Vijay Chauhan
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Publication number: 20160283244Abstract: In accordance with some embodiments of the present invention, a branch prediction unit for an embedded controller may be placed in association with the instruction fetch unit instead of the decode stage. In addition, the branch prediction unit may include no branch predictor. Also, the return address stack may be associated with the instruction decode stage and is structurally separate from the branch prediction unit. In some cases, this arrangement reduces the area of the branch prediction unit, as well as power consumption.Type: ApplicationFiled: June 7, 2016Publication date: September 29, 2016Inventors: Xiaowei Jiang, Srihari Makineni, Zhen Fang, Dmitri Pavlov, Ravi Iyer
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Patent number: 9395994Abstract: In accordance with some embodiments of the present invention, a branch prediction unit for an embedded controller may be placed in association with the instruction fetch unit instead of the decode stage. In addition, the branch prediction unit may include no branch predictor. Also, the return address stack may be associated with the instruction decode stage and is structurally separate from the branch prediction unit. In some cases, this arrangement reduces the area of the branch prediction unit, as well as power consumption.Type: GrantFiled: December 30, 2011Date of Patent: July 19, 2016Assignee: Intel CorporationInventors: Xiaowei Jiang, Srihari Makineni, Zhen Fang, Dmitri Pavlov, Ravi Iyer
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Patent number: 9076888Abstract: Methods and structures are provided for full silicidation of recessed silicon. Silicon is provided within a trench. A mixture of metals is provided over the silicon in which one of the metals diffuses more readily in silicon than silicon does in the metal, and another of the metals diffuses less readily in silicon than silicon does in the metal. An exemplary mixture includes 80% nickel and 20% cobalt. The silicon within the trench is allowed to fully silicide without void formation, despite a relatively high aspect ratio for the trench. Among other devices, recessed access devices (RADs) can be formed by the method for memory arrays.Type: GrantFiled: December 21, 2006Date of Patent: July 7, 2015Assignee: Micron Technology, Inc.Inventors: Hasan Nejad, Thomas A. Figura, Gordon A. Haller, Ravi Iyer, John Mark Meldrim, Justin Harnish
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Publication number: 20140019736Abstract: In accordance with some embodiments of the present invention, a branch prediction unit for an embedded controller may be placed in association with the instruction fetch unit instead of the decode stage. In addition, the branch prediction unit may include no branch predictor. Also, the return address stack may be associated with the instruction decode stage and is structurally separate from the branch prediction unit. In some cases, this arrangement reduces the area of the branch prediction unit, as well as power consumption.Type: ApplicationFiled: December 30, 2011Publication date: January 16, 2014Inventors: Xiaowei Jiang, Srihari Makineni, Zhen Fang, Dmitri Pavlov, Ravi Iyer
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Publication number: 20130345152Abstract: Disclosed herein are expression vectors that encode cowpox virus protein CPXV014 and homologs thereof that are useful in inhibiting CD3/CD28 mediated T cell stimulation. Further disclosed are polypeptide compositions comprising CPXV014 and homologs thereof as well as methods of inhibiting CD3/CD28 mediated T cell stimulation using the polypeptide compositions.Type: ApplicationFiled: June 20, 2013Publication date: December 26, 2013Applicant: OREGON HEALTH & SCIENCE UNIVERSITYInventors: Klaus Frueh, David M. Edwards, Ravi Iyer, Dina Alzhanova
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Patent number: 8420170Abstract: Disclosed is a deposition process for forming a glass film. An embodiment comprising the steps of disposing a substrate in a chemical vapor deposition chamber and exposing the substrate surface to a SiO2 precursor gas, a carrier gas, and optionally a dopant gas in the presence of ozone and exposing the reaction volume of the gases above the substrate surface to a high intensity light source.Type: GrantFiled: July 26, 2010Date of Patent: April 16, 2013Assignee: Micron Technology, Inc.Inventors: Gurtej S. Sandhu, Ravi Iyer
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Patent number: 8349687Abstract: A transistor gate forming method includes forming a metal layer within a line opening and forming a fill layer within the opening over the metal layer. The fill layer is substantially selectively etchable with respect to the metal layer. A transistor structure includes a line opening, a dielectric layer within the opening, a metal layer over the dielectric layer within the opening, and a fill layer over the metal layer within the opening. The metal layer/fill layer combination exhibits less intrinsic less than would otherwise exist if the fill layer were replaced by an increased thickness of the metal layer. The inventions apply at least to 3-D transistor structures.Type: GrantFiled: December 23, 2010Date of Patent: January 8, 2013Assignee: Micron Technology, Inc.Inventors: Sanh D. Tang, Gordon A. Haller, Prashant Raghu, Ravi Iyer
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Patent number: 8202806Abstract: A method of fabricating an integrated circuit having reduced threshold voltage shift is provided. A nonconducting region is formed on the semiconductor substrate and active regions are formed on the semiconductor substrate. The active regions are separated by the nonconducting region. A barrier layer and a dielectric layer are deposited over the nonconducting region and over the active regions. Heat is applied to the integrated circuit causing the barrier layer to anneal.Type: GrantFiled: October 3, 2005Date of Patent: June 19, 2012Assignee: Micron Technology, Inc.Inventors: Randhir P.S. Thakur, Ravi Iyer, Howard Rhodes
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Patent number: 8089128Abstract: A transistor gate forming method includes forming a first and a second transistor gate. Each of the two gates includes a lower metal layer and an upper metal layer. The lower metal layer of the first gate originates from an as-deposited material exhibiting a work function the same as exhibited in an as-deposited material from which the lower metal layer of the second gate originates. However, the first gate's lower metal layer exhibits a modified work function different from a work function exhibited by the second gate's lower metal layer. The first gate's lower metal layer may contain less oxygen and/or carbon in comparison to the second gate's lower metal layer. The first gate's lower metal layer may contain more nitrogen in comparison to the second gate's lower metal layer. The first gate may be a n-channel gate and the second gate may be a p-channel gate.Type: GrantFiled: April 15, 2009Date of Patent: January 3, 2012Assignee: Micron Technology, Inc.Inventors: D. V. Nirmal Ramaswamy, Ravi Iyer
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Patent number: 8036246Abstract: In general, in one aspect, the disclosures describes a method that includes receiving multiple ingress Internet Protocol packets, each of the multiple ingress Internet Protocol packets having an Internet Protocol header and a Transmission Control Protocol segment having a Transmission Control Protocol header and a Transmission Control Protocol payload, where the multiple packets belonging to a same Transmission Control Protocol/Internet Protocol flow. The method also includes preparing an Internet Protocol packet having a single Internet Protocol header and a single Transmission Control Protocol segment having a single Transmission Control Protocol header and a single payload formed by a combination of the Transmission Control Protocol segment payloads of the multiple Internet Protocol packets. The method further includes generating a signal that causes receive processing of the Internet Protocol packet.Type: GrantFiled: September 30, 2009Date of Patent: October 11, 2011Assignee: Intel CorporationInventors: Srihari Makineni, Ravi Iyer, Dave Minturn, Sujoy Sen, Donald Newell, Li Zhao
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Patent number: 7977236Abstract: Methods and structures are provided for full silicidation of recessed silicon. Silicon is provided within a trench. A mixture of metals is provided over the silicon in which one of the metals diffuses more readily in silicon than silicon does in the metal, and another of the metals diffuses less readily in silicon than silicon does in the metal. An exemplary mixture includes 80% nickel and 20% cobalt. The silicon within the trench is allowed to fully silicide without void formation, despite a relatively high aspect ratio for the trench. Among other devices, recessed access devices (RADs) can be formed by the method for memory arrays.Type: GrantFiled: June 2, 2009Date of Patent: July 12, 2011Assignee: Micron Technology, Inc.Inventors: Hasan Nejad, Thomas A. Figura, Gordon A. Haller, Ravi Iyer, John Mark Meldrim, Justin Harnish
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Publication number: 20110092062Abstract: A transistor gate forming method includes forming a metal layer within a line opening and forming a fill layer within the opening over the metal layer. The fill layer is substantially selectively etchable with respect to the metal layer. A transistor structure includes a line opening, a dielectric layer within the opening, a metal layer over the dielectric layer within the opening, and a fill layer over the metal layer within the opening. The metal layer/fill layer combination exhibits less intrinsic less than would otherwise exist if the fill layer were replaced by an increased thickness of the metal layer. The inventions apply at least to 3-D transistor structures.Type: ApplicationFiled: December 23, 2010Publication date: April 21, 2011Applicant: Micron Technology, Inc.Inventors: Sanh D. Tang, Gordon A. Haller, Prashant Raghu, Ravi Iyer
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Publication number: 20110090920Abstract: In general, in one aspect, the disclosures describes a method that includes receiving multiple ingress Internet Protocol packets, each of the multiple ingress Internet Protocol packets having an Internet Protocol header and a Transmission Control Protocol segment having a Transmission Control Protocol header and a Transmission Control Protocol payload, where the multiple packets belonging to a same Transmission Control Protocol/Internet Protocol flow. The method also includes preparing an Internet Protocol packet having a single Internet Protocol header and a single Transmission Control Protocol segment having a single Transmission Control Protocol header and a single payload formed by a combination of the Transmission Control Protocol segment payloads of the multiple Internet Protocol packets. The method further includes generating a signal that causes receive processing of the Internet Protocol packet.Type: ApplicationFiled: December 29, 2010Publication date: April 21, 2011Inventors: Srihari Makineni, Ravi Iyer, Dave Minturn, Sujoy Sen, Donald Newell, Li Zhao
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Patent number: 7867845Abstract: A transistor gate forming method includes forming a metal layer within a line opening and forming a fill layer within the opening over the metal layer. The fill layer is substantially selectively etchable with respect to the metal layer. A transistor structure includes a line opening, a dielectric layer within the opening, a metal layer over the dielectric layer within the opening, and a fill layer over the metal layer within the opening. The metal layer/fill layer combination exhibits less intrinsic less than would otherwise exist if the fill layer were replaced by an increased thickness of the metal layer. The inventions apply at least to 3-D transistor structures.Type: GrantFiled: September 1, 2005Date of Patent: January 11, 2011Assignee: Micron Technology, Inc.Inventors: Sanh D. Tang, Gordon A. Haller, Prashant Raghu, Ravi Iyer
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Publication number: 20100285238Abstract: Disclosed is a deposition process for forming a glass film. An embodiment comprising the steps of disposing a substrate in a chemical vapor deposition chamber and exposing the substrate surface to a SiO2 precursor gas, a carrier gas, and optionally a dopant gas in the presence of ozone and exposing the reaction volume of the gases above the substrate surface to a high intensity light source.Type: ApplicationFiled: July 26, 2010Publication date: November 11, 2010Inventors: Gurtej S. Sandhu, Ravi Iyer
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Patent number: 7763327Abstract: A CVD ozone (O3) deposition process, with the preferred embodiment comprising the steps of disposing a substrate in a chemical vapor deposition chamber and exposing the substrate surface to a SiO2 precursor gas, a carrier gas, and optionally a dopant gas in the presence of ozone and exposing the reaction volume of the 5 gases above the substrate surface to a high intensity light source, to increase the functional atomic oxygen concentration and reduce the fixed charge in the deposited films.Type: GrantFiled: July 27, 2005Date of Patent: July 27, 2010Assignee: Micron Technology, Inc.Inventors: Gurtej S. Sandhu, Ravi Iyer
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Patent number: 7659560Abstract: A transistor gate forming method includes forming a metal layer within a line opening and forming a fill layer within the opening over the metal layer. The fill layer is substantially selectively etchable with respect to the metal layer. A transistor structure includes a line opening, a dielectric layer within the opening, a metal layer over the dielectric layer within the opening, and a fill layer over the metal layer within the opening. The metal layer/fill layer combination exhibits less intrinsic less than would otherwise exist if the fill layer were replaced by an increased thickness of the metal layer. The inventions apply at least to 3-D transistor structures.Type: GrantFiled: March 8, 2007Date of Patent: February 9, 2010Assignee: Micron Technology, Inc.Inventors: Sanh D. Tang, Gordon A. Haller, Prashant Raghu, Ravi Iyer
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Publication number: 20100020819Abstract: In general, in one aspect, the disclosures describes a method that includes receiving multiple ingress Internet Protocol packets, each of the multiple ingress Internet Protocol packets having an Internet Protocol header and a Transmission Control Protocol segment having a Transmission Control Protocol header and a Transmission Control Protocol payload, where the multiple packets belonging to a same Transmission Control Protocol/Internet Protocol flow. The method also includes preparing an Internet Protocol packet having a single Internet Protocol header and a single Transmission Control Protocol segment having a single Transmission Control Protocol header and a single payload formed by a combination of the Transmission Control Protocol segment payloads of the multiple Internet Protocol packets. The method further includes generating a signal that causes receive processing of the Internet Protocol packet.Type: ApplicationFiled: September 30, 2009Publication date: January 28, 2010Inventors: Srihari Makineni, Ravi Iyer, Dave Minturn, Sujoy Sen, Donald Newell, Li Zhao
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Patent number: 7642204Abstract: In one aspect, the invention includes a method of forming an insulating material comprising: a) providing a substrate within a reaction chamber; b) providing reactants comprising a Si, F and ozone within the reaction chamber; and c) depositing an insulating material comprising fluorine, silicon and oxygen onto the substrate from the reactants. In another aspect, the invention includes a method of forming a boron-doped silicon oxide having Si—F bonds, comprising: a) providing a substrate within a reaction chamber; b) providing reactants comprising Triethoxy fluorosilane, a boron-containing precursor, and ozone within the reaction chamber; and c) depositing a boron-doped silicon oxide having Si—F bonds onto the substrate from the reactants.Type: GrantFiled: January 30, 2004Date of Patent: January 5, 2010Assignee: Micron Technology, Inc.Inventors: Anand Srinivasan, Gurtej Sandhu, Ravi Iyer