Abstract: A method for depositing highly conformal silicate glass layers via chemical vapor deposition through the reaction of TEOS and O3 is provided, comprising placing an in-process semiconductor wafer having multiple surface constituents in a plasma-enhanced chemical vapor deposition chamber.

Abstract: A method for use in the fabrication of a gate electrode includes providing a gate oxide layer and forming a titanium boride layer on the oxide layer. An insulator cap layer is formed on the titanium boride layer and thereafter, the gate electrode is formed from the titanium boride layer. A barrier layer may be formed on the oxide layer prior to forming the titanium boride layer with the gate electrode being formed from the barrier layer and the titanium boride layer. Further, a polysilicon layer may be formed on the gate oxide layer prior to forming the titanium boride layer with the gate electrode being formed from the titanium boride layer and the polysilicon layer. Yet further, a polysilicon layer may be formed on the gate oxide layer and a barrier layer formed on the polysilicon layer prior to forming the titanium boride layer. The gate electrode is then formed from the polysilicon layer, the barrier layer, and the titanium boride layer.

Abstract: An interlevel dielectric structure includes first and second dielectric layers between which are located lines of a conductive material with a dielectric material in spaces between the lines of conductive material, with the lower surface of the dielectric material extending lower than the lower surface of lines of conductive material adjacent thereto, and the upper surface of the dielectric material extending higher than the upper surface of conductive material adjacent thereto, thus reducing fringe and total capacitance between the lines of conductive material. The dielectric material, which has a dielectric constant of less than about 3.6, does not extend directly above the upper surface of the lines of conductive material, allowing formation of subsequent contacts down to the lines of conductive material without exposing the dielectric material to further processing. Various methods for forming the interlevel dielectric structure are disclosed.

Abstract: The invention includes integrated circuitry having an electrically insulative layer over a substrate and an opening within the electrically insulative layer. The opening has a periphery defined at least in part by a bottom surface and a sidewall surface. A first titanium layer is disposed within the opening in contact with the bottom surface and is thicker along the bottom surface than along the sidewall. A layer of TiN is provided over the first titanium layer along the bottom surface and along the sidewall surface of the opening, and a second layer of titanium is disposed over the electrically insulative layer but substantially not within the opening. The second titanium layer has a thickness of less then 50 Å along the sidewall surface and over the bottom surface. An aluminum-comprising layer is within the opening and over the second layer.

Abstract: A method for use in the fabrication of a gate electrode includes providing a gate oxide layer and forming a titanium boride layer on the oxide layer. An insulator cap layer is formed on the titanium boride layer and thereafter, the gate electrode is formed from the titanium boride layer. A barrier layer may be formed on the oxide layer prior to forming the titanium boride layer with the gate electrode being formed from the barrier layer and the titanium boride layer. Further, a polysilicon layer may be formed on the gate oxide layer prior to forming the titanium boride layer with the gate electrode being formed from the titanium boride layer and the polysilicon layer. Yet further, a polysilicon layer may be formed on the gate oxide layer and a barrier layer formed on the polysilicon layer prior to forming the titanium boride layer. The gate electrode is then formed from the polysilicon layer, the barrier layer, and the titanium boride layer.

Abstract: A method for depositing highly conformal silicate glass layers via chemical vapor deposition through the reaction of TEOS and O3 comprises placing an in-process semiconductor wafer having multiple surface constituents in a plasma-enhanced chemical vapor deposition chamber.

Abstract: Methods of forming insulating materials between conductive elements include forming a material adjacent a conductive electrical component comprising: partially vaporizing a mass to form a matrix adjacent the conductive electrical component, the matrix having at least one void within it. Other methods include forming a material between a pair of conductive electrical components comprising: forming a pair of conductive electrical components within a mass and separated by an expanse of the mass; forming at least one support member within the expanse of the mass, the support member not comprising a conductive interconnect; and vaporizing the expanse of the mass to a degree effective to form at least one void between the support member and each of the pair of conductive electrical components. Some embodiments include an insulating material adjacent a conductive electrical component, such material comprising a matrix and at least one void within the matrix.

Abstract: A method for depositing an aluminum film limits the growth of voids and notches in the aluminum film and forms and aluminum film with a reduced amount of voids and notches. The first step of the method is to form an underlying layer upon which is deposited an aluminum film having a first thickness. The surface of the aluminum film is then exposed to a passivation species which coats the aluminum grains and precipitates at the grain boundaries so as to prevent grain movement. The exposure of the aluminum film to the passivation species reduces void formation and coalescence of the voids. An aluminum layer having a second thickness is then deposited over the initially deposited aluminum layer. In a second embodiment of the invention, the passivation species is deposited with MOCVD and to form an electromigration-resistant alloy. A third embodiment involves multiple depositions of aluminum, with exposure to a passivation species conducted after each deposition.

Abstract: In one aspect, the invention includes a method of forming an insulating material comprising: a) providing a substrate within a reaction chamber; b) providing reactants comprising a Si, F and ozone within the reaction chamber; and c) depositing an insulating material comprising fluorine, silicon and oxygen onto the substrate from the reactants. In another aspect, the invention includes a method of forming a boron-doped silicon oxide having Si-F bonds, comprising: a) providing a substrate within a reaction chamber; b) providing reactants comprising Triethoxy fluorosilane, a boron-containing precursor, and ozone within the reaction chamber; and c) depositing a boron-doped silicon oxide having Si—F bonds onto the substrate from the reactants.

Abstract: A method for depositing highly conformal silicate glass layers via chemical vapor deposition through the reaction of TEOS and O3 comprises placing an in-process semiconductor wafer having multiple surface constituents in a plasma-enhanced chemical vapor deposition chamber.

Abstract: A planarization process for filling spaces between patterned metal features formed over a surface of a semiconductor substrate. The patterned metal features are preferably coated with a dielectric barrier. The dielectric barrier is coated with an material that expands during oxidation or nitridization to a thickness about half the depth of the space between metallized features. The layer is then plasma oxidized using an RF or ECR plasma at low temperature with an oxygen ambient. Alternatively, the layer is plasma nitridized at low temperature. The plasma oxidation or nitridization is continued until the expandable material is converted to a dielectric and has expanded to fill the space between patterned metal features. Optionally, the process can be followed by a mechanical or chemical mechanical planarization step.

Abstract: The fixed charge in a borophosphosilicate glass insulating film deposited on a semiconductor device is reduced by reacting an organic precursor such as TEOS with O3. When done at temperatures higher than approximately 480 degrees C., the carbon level in the resulting film appears to be reduced, resulting in a higher threshold voltage for field transistor devices.

Abstract: A new process for depositing titanium metal layers via chemical vapor deposition is disclosed. The process provides deposited titanium layers having a high degree of conformality, even in trenches and contact openings having aspect ratios greater than 1:5.

Abstract: Various embodiments of the invention described herein reduce contact resistance to a silicon-containing material using a first refractory metal material overlying the silicon-containing material and a second refractory metal material overlying the first refractory metal material. Each refractory metal material is a conductive material containing a refractory metal and an impurity. The first refractory metal material is a metal-rich material, containing a level of its impurity at less than a stoichiometric level. The second refractory metal material has a lower affinity for the impurities than does the first refractory metal material. The second refractory metal material can thus serve as an impurity donor during an anneal or other exposure to heat.

Abstract: In one aspect, the invention includes a method of forming an insulating material comprising: a) providing a substrate within a reaction chamber; b) providing reactants comprising a Si, F and ozone within the reaction chamber; and c) depositing an insulating material comprising fluorine, silicon and oxygen onto the substrate from the reactants. In another aspect, the invention includes a method of forming a boron-doped silicon oxide having Si—F bonds, comprising: a) providing a substrate within a reaction chamber; b) providing reactants comprising Triethoxy fluorosilane, a boron-containing precursor, and ozone within the reaction chamber; and c) depositing a boron-doped silicon oxide having Si—F bonds onto the substrate from the reactants.

Abstract: Various embodiments of the invention described herein reduce contact resistance to a silicon-containing material using a first refractory metal material overlying the silicon-containing material and a second refractory metal material overlying the first refractory metal material. Each refractory metal material is a conductive material containing a refractory metal and an impurity. The first refractory metal material is a metal-rich material, containing a level of its impurity at less than a stoichiometric level. The second refractory metal material has a lower affinity for the impurities than does the first refractory metal material. The second refractory metal material can thus serve as an impurity donor during an anneal or other exposure to heat.

Abstract: A method for forming a gate stack which minimizes or eliminates damage to the gate dielectric layer and/or silicon substrate during the gate stack formation by the reduction of the temperature during formation. The temperature reduction prevents the formation of silicon clusters within the metallic silicide film in the gate stack which has been found to cause damage during the gate etch step. The present invention also includes methods for dispersing silicon clusters prior to the gate etch step.

Abstract: A method for forming a gate stack which minimizes or eliminates damage to the gate dielectric layer and/or silicon substrate during the gate stack formation by the reduction of the temperature during formation. The temperature reduction prevents the formation of silicon clusters within the metallic silicide film in the gate stack which has been found to cause damage during the gate etch step. The present invention also includes methods for dispersing silicon clusters prior to the gate etch step.

Abstract: The fixed charge in a borophosphosilicate glass insulating film deposited on a semiconductor device is reduced by reacting an organic precursor such as TEOS with O3. When done at temperatures higher than approximately 480 degrees C., the carbon level in the resulting film appears to be reduced, resulting in a higher threshold voltage for field transistor devices.

Abstract: A new process for depositing titanium metal layers via chemical vapor deposition is disclosed. The process provides deposited titanium layers having a high degree of conformality, even in trenches and contact openings having aspect ratios greater than 1:5. The reaction gases for the improved process are titanium tetrachloride and a hydrocarbon gas, which for a preferred embodiment of the process is methane. The reaction is carried out in a plasma environment created by a radio frequency source greater than 10 KHz. The key to obtaining titanium metal as a reaction product, rather than titanium carbide, is to set the plasma-sustaining electrical power within a range that will remove just one hydrogen atom from each molecule of the hydrocarbon gas. In a preferred embodiment of the process, highly reactive methyl radicals (CH3-) are formed from methane gas. These radicals attack the titanium-chlorine bonds of the tetrachloride molecule and form chloromethane, which is evacuated from the chamber as it is formed.