Patents by Inventor Ravi Joshi
Ravi Joshi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20210129121Abstract: A novel catalyst composition and its use in the oligomerization reaction converting a portion of a C2 to C5+ alkene feed stream to C4 to C6+ olefin derivatives. The catalyst comprises a Group VIII noble metal selected from the group consisting of nickel, iron, cobalt, and combinations thereof, on a support. The support can be silica, silicon dioxide, titanium dioxide, metal modified silica, silica-pillared clays, silica-pillared micas, metal oxide modified silica-pillared mica, silica-pillared tetrasilicic mica, silica-pillared taeniolite, zeolite, molecular sieve, and combinations thereof. The catalyst composition is an active and selective catalyst for the catalytic oligomerization of alkenes to olefins and olefin derivatives.Type: ApplicationFiled: July 31, 2018Publication date: May 6, 2021Applicant: PURDUE RESEARCH FOUNDATIONInventors: Rajamani Gounder, Ravi Joshi
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Patent number: 10910309Abstract: In various embodiments a method for manufacturing a metallization layer on a substrate is provided, wherein the method may include providing a structured layer of a catalyst material on the substrate, the catalyst material may include a first layer of material arranged over the substrate and a second layer of material arranged over the first layer of material, wherein the structured layer of catalyst material having a first set of regions including the catalyst material over the substrate and a second set of regions free of the catalyst material over the substrate, and forming a plurality of groups of nanotubes over the substrate, each group of the plurality of groups of nanotubes includes a plurality of nanotubes formed over a respective region in the first set of regions.Type: GrantFiled: September 1, 2017Date of Patent: February 2, 2021Assignee: Infineon Technologies AGInventors: Ravi Joshi, Juergen Steinbrenner
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Publication number: 20210025648Abstract: A fluid delivery system for an appliance includes a fluid line in selective communication with a fluid source. A shelf defines a fill zone positioned below an underside of the shelf. A shelf spigot is coupled with the fluid line and disposed proximate the underside of the shelf and over the fill zone. A fluid level sensor is positioned in communication with the fill zone. The fluid level sensor is also in communication with a controller that regulates a flow of fluid through the shelf spigot.Type: ApplicationFiled: October 14, 2020Publication date: January 28, 2021Applicant: WHIRLPOOL CORPORATIONInventors: Kaito Choy, Ravi Joshi, Vikas C. Mruthyunjaya, Henrique Keiji Arai Yamaki
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Patent number: 10837698Abstract: A fluid delivery system for an appliance includes a fluid line in selective communication with a fluid source. A shelf defines a fill zone positioned below an underside of the shelf. A shelf spigot is coupled with the fluid line and disposed proximate the underside of the shelf and over the fill zone. A fluid level sensor is positioned in communication with the fill zone. The fluid level sensor is also in communication with a controller that regulates a flow of fluid through the shelf spigot.Type: GrantFiled: December 29, 2018Date of Patent: November 17, 2020Assignee: Whirlpool CorporationInventors: Kaito Choy, Ravi Joshi, Vikas C. Mruthyunjaya, Henrique Keiji Arai Yamaki
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Publication number: 20200208904Abstract: A fluid delivery system for an appliance includes a fluid line in selective communication with a fluid source. A shelf defines a fill zone positioned below an underside of the shelf. A shelf spigot is coupled with the fluid line and disposed proximate the underside of the shelf and over the fill zone. A fluid level sensor is positioned in communication with the fill zone. The fluid level sensor is also in communication with a controller that regulates a flow of fluid through the shelf spigot.Type: ApplicationFiled: December 29, 2018Publication date: July 2, 2020Applicant: WHIRLPOOL CORPORATIONInventors: Kaito Choy, Ravi Joshi, Vikas C. Mruthyunjaya, Henrique Keiji Arai Yamaki
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Patent number: 10325803Abstract: According to various embodiments, a semiconductor wafer may include: a semiconductor body including an integrated circuit structure; and at least one tetrahedral amorphous carbon layer formed at least one of over or in the integrated circuit structure, the at least one tetrahedral amorphous carbon layer may include a substance amount fraction of sp3-hybridized carbon of larger than approximately 0.4 and a substance amount fraction of hydrogen smaller than approximately 0.1.Type: GrantFiled: May 3, 2018Date of Patent: June 18, 2019Assignee: Infineon Technologies AGInventors: Matthias Kuenle, Gerhard Schmidt, Martin Sporn, Markus Kahn, Juergen Steinbrenner, Ravi Joshi
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Publication number: 20180247857Abstract: According to various embodiments, a semiconductor wafer may include: a semiconductor body including an integrated circuit structure; and at least one tetrahedral amorphous carbon layer formed at least one of over or in the integrated circuit structure, the at least one tetrahedral amorphous carbon layer may include a substance amount fraction of sp3-hybridized carbon of larger than approximately 0.4 and a substance amount fraction of hydrogen smaller than approximately 0.1.Type: ApplicationFiled: May 3, 2018Publication date: August 30, 2018Inventors: Matthias KUENLE, Gerhard SCHMIDT, Martin SPORN, Markus KAHN, Juergen STEINBRENNER, Ravi JOSHI
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Patent number: 10043750Abstract: In various embodiments a method for manufacturing a metallization layer on a substrate is provided, wherein the method may include forming a plurality of groups of nanotubes over a substrate, wherein the groups of nanotubes may be arranged such that a portion of the substrate is exposed and forming metal over the exposed portion of the substrate between the plurality of groups of nanotubes.Type: GrantFiled: June 15, 2015Date of Patent: August 7, 2018Assignee: Infineon Technologies AGInventors: Ravi Joshi, Juergen Steinbrenner
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Patent number: 9984915Abstract: According to various embodiments, a semiconductor wafer may include: a semiconductor body including an integrated circuit structure; and at least one tetrahedral amorphous carbon layer formed at least one of over or in the integrated circuit structure, the at least one tetrahedral amorphous carbon layer may include a substance amount fraction of sp3-hybridized carbon of larger than approximately 0.4 and a substance amount fraction of hydrogen smaller than approximately 0.1.Type: GrantFiled: May 30, 2014Date of Patent: May 29, 2018Assignee: Infineon Technologies AGInventors: Matthias Kuenle, Gerhard Schmidt, Martin Sporn, Markus Kahn, Juergen Steinbrenner, Ravi Joshi
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Patent number: 9917170Abstract: A method of forming a contact structure includes providing a silicon-carbide substrate having a highly doped silicon-carbide contact region formed in the substrate and extending to a main surface of the substrate. A carbon-based contact region is formed which is in direct contact with the highly doped silicon-carbide contact region and which extends to the main surface. A conductor is formed on the carbon-based contact region such that the carbon-based contact region is interposed between the conductor and the highly doped silicon-carbide contact region. A thermal budget for forming the carbon-based contact region is maintained below a level that induces metal silicidization of the highly doped silicon-carbide contact region.Type: GrantFiled: April 22, 2016Date of Patent: March 13, 2018Assignee: Infineon Technologies AGInventors: Ravi Joshi, Romain Esteve, Markus Kahn, Gerald Unegg
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Patent number: 9899325Abstract: In various embodiments a method of forming a device is provided. The method includes forming a metal layer over a substrate and forming at least one barrier layer. The forming of the barrier layer includes depositing a solution comprising a metal complex over the substrate and at least partially decomposing of the ligand of the metal complex.Type: GrantFiled: August 7, 2014Date of Patent: February 20, 2018Assignee: INFINEON TECHNOLOGIES AGInventor: Ravi Joshi
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Publication number: 20180012836Abstract: In various embodiments a method for manufacturing a metallization layer on a substrate is provided, wherein the method may include providing a structured layer of a catalyst material on the substrate, the catalyst material may include a first layer of material arranged over the substrate and a second layer of material arranged over the first layer of material, wherein the structured layer of catalyst material having a first set of regions including the catalyst material over the substrate and a second set of regions free of the catalyst material over the substrate, and forming a plurality of groups of nanotubes over the substrate, each group of the plurality of groups of nanotubes includes a plurality of nanotubes formed over a respective region in the first set of regions.Type: ApplicationFiled: September 1, 2017Publication date: January 11, 2018Inventors: Ravi Joshi, Juergen Steinbrenner
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Publication number: 20170309720Abstract: A method of forming a contact structure includes providing a silicon-carbide substrate having a highly doped silicon-carbide contact region formed in the substrate and extending to a main surface of the substrate. A carbon-based contact region is formed which is in direct contact with the highly doped silicon-carbide contact region and which extends to the main surface. A conductor is formed on the carbon-based contact region such that the carbon-based contact region is interposed between the conductor and the highly doped silicon-carbide contact region. A thermal budget for forming the carbon-based contact region is maintained below a level that induces metal silicidization of the highly doped silicon-carbide contact region.Type: ApplicationFiled: April 22, 2016Publication date: October 26, 2017Inventors: Ravi Joshi, Romain Esteve, Markus Kahn, Gerald Unegg
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Patent number: 9768273Abstract: In one aspect, a method of forming a trench in a semiconductor material includes forming a first dielectric layer on a semiconductor substrate. The first dielectric layer includes first openings. An epitaxial layer is grown on the semiconductor substrate by an epitaxial lateral overgrowth process. The first openings are filled by the epitaxial layer and the epitaxial layer is grown onto adjacent portions of the first dielectric layer so that part of the first dielectric layer is uncovered by the epitaxial layer and a gap forms between opposing sidewalls of the epitaxial layer over the part of the first dielectric layer that is uncovered by the epitaxial layer. The gap defines a first trench in the epitaxial layer that extends to the first dielectric layer.Type: GrantFiled: June 20, 2016Date of Patent: September 19, 2017Assignee: Infineon Technologies Austria AGInventors: Ravi Joshi, Johannes Baumgartl, Martin Poelzl, Matthias Kuenle, Juergen Steinbrenner, Andreas Haghofer, Christoph Gruber, Georg Ehrentraut
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Patent number: 9704800Abstract: In various embodiments a method for manufacturing a metallization layer on a substrate is provided, wherein the method may include forming a plurality of groups of nanotubes over a substrate, wherein the groups of nanotubes may be arranged such that a portion of the substrate is exposed and forming metal over the exposed portion of the substrate between the plurality of groups of nanotubes.Type: GrantFiled: August 27, 2015Date of Patent: July 11, 2017Assignee: INFINEON TECHNOLOGIES AGInventors: Ravi Joshi, Juergen Steinbrenner
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Publication number: 20170011927Abstract: A method for depositing an insulating layer includes performing a primary deposition over a sidewall of a feature by depositing a layer of silicate glass using a silicon source at a first flow rate and a dopant source at a second flow rate. A ratio of the flow of the dopant source to the flow of the silicon source is a first ratio. The method further includes performing a secondary deposition over the sidewall of a feature by increasing the flow of the silicon source relative to the flow of the dopant source. The ratio of the flow of the dopant source to the flow of the silicon source is a second ratio lower than the first ratio, and stopping the flow of the silicon source after performing the secondary deposition. A reflow process is performed after stopping the flow. A variation in thickness of the layer of silicate glass over the sidewall of a feature after the reflow process is between 1% to 20%.Type: ApplicationFiled: September 22, 2016Publication date: January 12, 2017Inventors: Juergen Steinbrenner, Markus Kahn, Helmut Schoenherr, Ravi Joshi, Heimo Hofer, Martin Poelzl, Harald Huetter
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Publication number: 20160308028Abstract: In one aspect, a method of forming a trench in a semiconductor material includes forming a first dielectric layer on a semiconductor substrate. The first dielectric layer includes first openings. An epitaxial layer is grown on the semiconductor substrate by an epitaxial lateral overgrowth process. The first openings are filled by the epitaxial layer and the epitaxial layer is grown onto adjacent portions of the first dielectric layer so that part of the first dielectric layer is uncovered by the epitaxial layer and a gap forms between opposing sidewalls of the epitaxial layer over the part of the first dielectric layer that is uncovered by the epitaxial layer. The gap defines a first trench in the epitaxial layer that extends to the first dielectric layer.Type: ApplicationFiled: June 20, 2016Publication date: October 20, 2016Inventors: Ravi Joshi, Johannes Baumgartl, Martin Poelzl, Matthias Kuenle, Juergen Steinbrenner, Andreas Haghofer, Christoph Gruber, Georg Ehrentraut
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Patent number: 9455136Abstract: A method for depositing an insulating layer includes performing a primary deposition over a sidewall of a feature by depositing a layer of silicate glass using a silicon source at a first flow rate and a dopant source at a second flow rate. A ratio of the flow of the dopant source to the flow of the silicon source is a first ratio. The method further includes performing a secondary deposition over the sidewall of a feature by increasing the flow of the silicon source relative to the flow of the dopant source. The ratio of the flow of the dopant source to the flow of the silicon source is a second ratio lower than the first ratio, and stopping the flow of the silicon source after performing the secondary deposition. A reflow process is performed after stopping the flow. A variation in thickness of the layer of silicate glass over the sidewall of a feature after the reflow process is between 1% to 20%.Type: GrantFiled: January 23, 2015Date of Patent: September 27, 2016Assignee: Infineon Technologies Austria AGInventors: Juergen Steinbrenner, Markus Kahn, Helmut Schoenherr, Ravi Joshi, Heimo Hofer, Martin Poelzl, Harald Huetter
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Publication number: 20160218002Abstract: A method for depositing an insulating layer includes performing a primary deposition over a sidewall of a feature by depositing a layer of silicate glass using a silicon source at a first flow rate and a dopant source at a second flow rate. A ratio of the flow of the dopant source to the flow of the silicon source is a first ratio. The method further includes performing a secondary deposition over the sidewall of a feature by increasing the flow of the silicon source relative to the flow of the dopant source. The ratio of the flow of the dopant source to the flow of the silicon source is a second ratio lower than the first ratio, and stopping the flow of the silicon source after performing the secondary deposition. A reflow process is performed after stopping the flow. A variation in thickness of the layer of silicate glass over the sidewall of a feature after the reflow process is between 1% to 20%.Type: ApplicationFiled: January 23, 2015Publication date: July 28, 2016Inventors: Juergen Steinbrenner, Markus Kahn, Helmut Schoenherr, Ravi Joshi, Heimo Hofer, Martin Poelzl, Harald Huetter
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Patent number: 9379196Abstract: In one aspect, a method of forming a trench in a semiconductor material includes forming a first dielectric layer on a semiconductor substrate. The first dielectric layer includes first openings. An epitaxial layer is grown on the semiconductor substrate by an epitaxial lateral overgrowth process. The first openings are filled by the epitaxial layer and the epitaxial layer is grown onto adjacent portions of the first dielectric layer so that part of the first dielectric layer is uncovered by the epitaxial layer and a gap forms between opposing sidewalls of the epitaxial layer over the part of the first dielectric layer that is uncovered by the epitaxial layer. The gap defines a first trench in the epitaxial layer that extends to the first dielectric layer.Type: GrantFiled: February 6, 2014Date of Patent: June 28, 2016Assignee: Infineon Technologies Austria AGInventors: Ravi Joshi, Johannes Baumgartl, Martin Poelzl, Matthias Kuenle, Juergen Steinbrenner, Andreas Haghofer, Christoph Gruber, Georg Ehrentraut