Patents by Inventor Ravi Kanth Kolan
Ravi Kanth Kolan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9704726Abstract: A structural member for use in semiconductor packaging is disclosed. The structural member includes a plurality of packaging regions to facilitate packaging dies in, for example, a wafer format. A packaging region has a die attach region surrounded by a peripheral region. A die is attached to the die attach region. In one aspect, the die attach region has opening through the surfaces of the structural member for accommodating a die. Through-vias disposed are in the peripheral regions. The structural member reduces warpage that can occur during curing of the mold compound used in encapsulating the dies. In another aspect, the die attach region does not have an opening. In such cases, the structural member serves as an interposer between the die and a substrate.Type: GrantFiled: September 18, 2015Date of Patent: July 11, 2017Assignee: UTAC HEADQUARTERS PTE. LTD.Inventors: Chin Hock Toh, Yi Sheng Anthony Sun, Xue Ren Zhang, Ravi Kanth Kolan
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Publication number: 20160005629Abstract: A structural member for use in semiconductor packaging is disclosed. The structural member includes a plurality of packaging regions to facilitate packaging dies in, for example, a wafer format. A packaging region has a die attach region surrounded by a peripheral region. A die is attached to the die attach region. In one aspect, the die attach region has opening through the surfaces of the structural member for accommodating a die. Through-vias disposed are in the peripheral regions. The structural member reduces warpage that can occur during curing of the mold compound used in encapsulating the dies. In another aspect, the die attach region does not have an opening. In such cases, the structural member serves as an interposer between the die and a substrate.Type: ApplicationFiled: September 18, 2015Publication date: January 7, 2016Inventors: Chin Hock TOH, Yi Sheng Anthony SUN, Xue Ren ZHANG, Ravi Kanth KOLAN
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Patent number: 9142487Abstract: A structural member for use in semiconductor packaging is disclosed. The structural member includes a plurality of packaging regions to facilitate packaging dies in, for example, a wafer format. A packaging region has a die attach region surrounded by a peripheral region. A die is attached to the die attach region. In one aspect, the die attach region has opening through the surfaces of the structural member for accommodating a die. Through-vias disposed are in the peripheral regions. The structural member reduces warpage that can occur during curing of the mold compound used in encapsulating the dies. In another aspect, the die attach region does not have an opening. In such cases, the structural member serves as an interposer between the die and a substrate.Type: GrantFiled: January 9, 2013Date of Patent: September 22, 2015Assignee: UNITED TEST AND ASSEMBLY CENTER LTD.Inventors: Chin Hock Toh, Yi Sheng Anthony Sun, Xue Ren Zhang, Ravi Kanth Kolan
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Patent number: 8772921Abstract: An interposer is presented. The interposer includes an interposer base having first and second surfaces. A redistribution layer is disposed on a first surface of the interposer base. The interposer has at least one interposer pad coupled to the redistribution layer. It also includes at least one interposer contact on the second surface. The interposer contact is electrically coupled to the interposer pad via the redistribution layer. The interposer also includes at least one interposer via through the interposer base for coupling the interposer contact to the redistribution layer. The interposer via includes reflowed conductive material of the interposer contact.Type: GrantFiled: January 10, 2012Date of Patent: July 8, 2014Assignee: United Test and Assembly Center Ltd.Inventors: Chin Hock Toh, Yao Huang Huang, Ravi Kanth Kolan, Wei Liang Yuan, Susanto Tanary, Yi Sheng Anthony Sun
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Patent number: 8741762Abstract: A method for preparing a die for packaging is disclosed. A die having first and second major surfaces is provided. Vias and a mask layer are formed on the first major surface of the die. The mask includes mask openings that expose the vias. The mask openings are filled with a conductive material. The method includes reflowing to at least partially fill the vias and contact openings to form via contacts in the vias and surface contacts in the mask openings.Type: GrantFiled: October 21, 2013Date of Patent: June 3, 2014Assignee: United Test and Assembly Center Ltd.Inventors: Hao Liu, Yi Sheng Anthony Sun, Ravi Kanth Kolan, Chin Hock Toh
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Publication number: 20140045301Abstract: A method for preparing a die for packaging is disclosed. A die having first and second major surfaces is provided. Vias and a mask layer are formed on the first major surface of the die. The mask includes mask openings that expose the vias. The mask openings are filled with a conductive material. The method includes reflowing to at least partially fill the vias and contact openings to form via contacts in the vias and surface contacts in the mask openings.Type: ApplicationFiled: October 21, 2013Publication date: February 13, 2014Applicant: United Test and Assembly Center Ltd.Inventors: Hao LIU, Yi Sheng Anthony SUN, Ravi Kanth KOLAN, Chin Hock TOH
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Patent number: 8586465Abstract: A method for preparing a die for packaging is disclosed. A die having first and second major surfaces is provided. Vias and a mask layer are formed on the first major surface of the die. The mask includes mask openings that expose the vias. The mask openings are filled with a conductive material. The method includes reflowing to at least partially fill the vias and contact openings to form via contacts in the vias and surface contacts in the mask openings.Type: GrantFiled: June 5, 2008Date of Patent: November 19, 2013Assignee: United Test and Assembly Center LtdInventors: Hao Liu, Yi Sheng Anthony Sun, Ravi Kanth Kolan, Chin Hock Toh
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Patent number: 8426246Abstract: A die that includes a substrate having a first and second major surface is disclosed. The die has at least one unfilled through via passing through the major surfaces of the substrate. The unfilled through via serves as a vent to release pressure generated during assembly.Type: GrantFiled: February 21, 2012Date of Patent: April 23, 2013Assignee: United Test and Assembly Center Ltd.Inventors: Chin Hock Toh, Hao Liu, Ravi Kanth Kolan
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Patent number: 8399985Abstract: A chip package includes a carrier having a first and a second major surface. The first major surface includes an active region surrounded by an inactive region. The chip package includes contact pads in the active region for mating with chip contacts of a chip. A support structure is disposed on the inactive region of the first major surface. The support structure forms a dam that surrounds the active region. When a chip or chip stack is mounted in the active region, spacing exists between the dam and the chip or chip stack. The spacing creates convention paths for heat dissipation.Type: GrantFiled: September 25, 2011Date of Patent: March 19, 2013Assignee: United Test And Assembly Center Ltd.Inventors: Ravi Kanth Kolan, Hao Liu, Chin Hock Toh
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Patent number: 8384203Abstract: A structural member for use in semiconductor packaging is disclosed. The structural member includes a plurality of packaging regions to facilitate packaging dies in, for example, a wafer format. A packaging region has a die attach region surrounded by a peripheral region. A die is attached to the die attach region. In one aspect, the die attach region has opening through the surfaces of the structural member for accommodating a die. Through-vias disposed are in the peripheral regions. The structural member reduces warpage that can occur during curing of the mold compound used in encapsulating the dies. In another aspect, the die attach region does not have an opening. In such cases, the structural member serves as an interposer between the die and a substrate.Type: GrantFiled: July 20, 2009Date of Patent: February 26, 2013Assignee: United Test and Assembly Center Ltd.Inventors: Chin Hock Toh, Yi Sheng Anthony Sun, Xue Ren Zhang, Ravi Kanth Kolan
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Publication number: 20120149150Abstract: A die that includes a substrate having a first and second major surface is disclosed. The die has at least one unfilled through via passing through the major surfaces of the substrate. The unfilled through via serves as a vent to release pressure generated during assembly.Type: ApplicationFiled: February 21, 2012Publication date: June 14, 2012Applicant: UNITED TEST AND ASSEMBLY CENTER LTD.Inventors: Chin Hock TOH, Hao LIU, Ravi Kanth KOLAN
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Publication number: 20120104628Abstract: An interposer is presented. The interposer includes an interposer base having first and second surfaces. A redistribution layer is disposed on a first surface of the interposer base. The interposer has at least one interposer pad coupled to the redistribution layer. It also includes at least one interposer contact on the second surface. The interposer contact is electrically coupled to the interposer pad via the redistribution layer. The interposer also includes at least one interposer via through the interposer base for coupling the interposer contact to the redistribution layer. The interposer via includes reflowed conductive material of the interposer contact.Type: ApplicationFiled: January 10, 2012Publication date: May 3, 2012Applicant: UNITED TEST AND ASSEMBLY CENTER LTD.Inventors: Chin Hock TOH, Yao Huang HUANG, Ravi Kanth KOLAN, Wei Liang YUAN, Susanto TANARY, Yi Sheng Anthony SUN
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Patent number: 8143719Abstract: A die that includes a substrate having a first and second major surface is disclosed. The die has at least one unfilled through via passing through the major surfaces of the substrate. The unfilled through via serves as a vent to release pressure generated during assembly.Type: GrantFiled: June 5, 2008Date of Patent: March 27, 2012Assignee: United Test and Assembly Center Ltd.Inventors: Chin Hock Toh, Hao Liu, Ravi Kanth Kolan
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Patent number: 8115292Abstract: An interposer is presented. The interposer includes an interposer base having first and second surfaces. A redistribution layer is disposed on a first surface of the interposer base. The interposer has at least one interposer pad coupled to the redistribution layer. It also includes at least one interposer contact on the second surface. The interposer contact is electrically coupled to the interposer pad via the redistribution layer. The interposer also includes at least one interposer via through the interposer base for coupling the interposer contact to the redistribution layer. The interposer via includes reflowed conductive material of the interposer contact.Type: GrantFiled: October 23, 2009Date of Patent: February 14, 2012Assignee: United Test and Assembly Center Ltd.Inventors: Chin Hock Toh, Yao Huang Huang, Ravi Kanth Kolan, Wei Liang Yuan, Susanto Tanary, Anthony Yi Sheng Sun
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Publication number: 20120018869Abstract: A chip package includes a carrier having a first and a second major surface. The first major surface includes an active region surrounded by an inactive region. The chip package includes contact pads in the active region for mating with chip contacts of a chip. A support structure is disposed on the inactive region of the first major surface. The support structure forms a dam that surrounds the active region. When a chip or chip stack is mounted in the active region, spacing exists between the dam and the chip or chip stack. The spacing creates convention paths for heat dissipation.Type: ApplicationFiled: September 25, 2011Publication date: January 26, 2012Applicant: UNITED TEST AND ASSEMBLY CENTER LTD.Inventors: Ravi Kanth KOLAN, Hao LIU, Chin Hock TOH
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Patent number: 8030761Abstract: A chip package includes a carrier having a first and a second major surface. The first major surface includes an active region surrounded by an inactive region. The chip package includes contact pads in the active region for mating with chip contacts of a chip. A support structure is disposed on the inactive region of the first major surface. The support structure forms a dam that surrounds the active region. When a chip or chip stack is mounted in the active region, spacing exists between the dam and the chip or chip stack. The spacing creates convention paths for heat dissipation.Type: GrantFiled: May 23, 2008Date of Patent: October 4, 2011Assignee: United Test and Assembly Center Ltd.Inventors: Ravi Kanth Kolan, Hao Liu, Chin Hock Toh
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Patent number: 7883938Abstract: A method of manufacturing a plurality of stacked die semiconductor packages, including: attaching a second silicon wafer to a first silicon wafer, wherein the second silicon wafer has a plurality of open vias; attaching a third silicon wafer to the second silicon wafer, wherein the third silicon wafer has a plurality of open vias, and the open vias of the second and third silicon wafers are aligned with one another; etching a bonding material that attaches the wafers from the aligned open vias; filling the aligned open vias with a conductor; forming conductive bumps at open ends of the aligned open vias; back grinding the first silicon wafer; separating the stacked semiconductor dies from each other; attaching the bump end of the stacked semiconductor dies onto a substrate; encapsulating the stacked semiconductor dies and substrate; and singulating the encapsulated assembly.Type: GrantFiled: May 21, 2008Date of Patent: February 8, 2011Assignee: United Test and Assembly Center Ltd.Inventors: Ravi Kanth Kolan, Anthony Sun Yi Sheng, Liu Hao, Toh Chin Hock
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Patent number: 7830006Abstract: A chip scale integrated circuit package includes an integrated circuit chip which has a first face and a second face. A plurality of pillar bumps are formed on the first face of the integrated circuit chip. An encapsulant material encapsulates the sides and the first face of the integrated circuit chip, and the pillar bumps. Upper ends of the pillar bumps remain free from encapsulant material and a substantially planar surface is formed by an upper surface of the encapsulant material and the upper ends of the pillar bumps. A plurality of solder balls are mounted on the substantially planar surface in locations corresponding to the upper ends of the pillar bumps.Type: GrantFiled: May 5, 2005Date of Patent: November 9, 2010Assignee: United Test and Assembly Center, Ltd.Inventors: Ravi Kanth Kolan, Hien Boon Tan, Anthony Yi Sheng Sun, Beng Kuan Lim, Krishnamoorthi Sivalingam
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Patent number: 7824960Abstract: A method of manufacturing a plurality of stacked die semiconductor packages, including: placing a phase change material between a top surface of a substrate and a bottom surface of a first die; placing a phase change material between a top surface of the first die and a bottom surface of a second die; wherein the first and second dies have a plurality of conductive protrusions on the bottom surfaces of the dies; wherein the first die has a plurality of conductive vias extending from its conductive protrusions, through the first die, to the top surface of the first die; wherein the conductive vias of said first die are in alignment with the conductive protrusions of the second die; and heating the dies and the substrate to cause the second die to become electrically interconnected to the first die and the first die to become electrically connected to the substrate.Type: GrantFiled: May 21, 2008Date of Patent: November 2, 2010Assignee: United Test and Assembly Center Ltd.Inventors: Liu Hao, Ravi Kanth Kolan
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Publication number: 20100109142Abstract: An interposer is presented. The interposer includes an interposer base having first and second surfaces. A redistribution layer is disposed on a first surface of the interposer base. The interposer has at least one interposer pad coupled to the redistribution layer. It also includes at least one interposer contact on the second surface. The interposer contact is electrically coupled to the interposer pad via the redistribution layer. The interposer also includes at least one interposer via through the interposer base for coupling the interposer contact to the redistribution layer. The interposer via includes reflowed conductive material of the interposer contact.Type: ApplicationFiled: October 23, 2009Publication date: May 6, 2010Applicant: UNITED TEST AND ASSEMBLY CENTER LTD.Inventors: Chin Hock Toh, Yao Huang Huang, Ravi Kanth Kolan, Wei Liang Yuan, Susanto Tanary, Yi Sheng Anthony Sun