Patents by Inventor Ravi Krishna

Ravi Krishna has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20060230265
    Abstract: A system uses a proxy server to authenticate a client with an authentication protocol that does not support caching. Rather than cache the client's authentication credentials, or access a client account manager for each network request generated by the client, the proxy server issues a cookie to an authenticated client and authenticate the client for subsequent request on the basis of the cookie.
    Type: Application
    Filed: April 8, 2005
    Publication date: October 12, 2006
    Inventor: Ravi Krishna
  • Patent number: 6397239
    Abstract: A multimedia execution unit configured to perform vectored floating point and integer instructions. The execution unit may include an add/subtract pipeline having far and close data paths. The far path is configured to handle effective addition operations and effective subtraction operations for operands having an absolute exponent difference greater than one. The close path is configured to handle effective subtraction operations for operands having an absolute exponent difference less than or equal to one. The close path is configured to generate two output values, wherein one output value is the first input operand plus an inverted version of the second input operand, while the second output value is equal to the first output value plus one. Selection of the first or second output value in the close path effectuates the round-to-nearest operation for the output of the adder.
    Type: Grant
    Filed: February 6, 2001
    Date of Patent: May 28, 2002
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Stuart F. Oberman, Norbert Juffa, Fred Weber, Krishnan Ramani, Ravi Krishna Cherukuri
  • Patent number: 6393554
    Abstract: A multiplier capable of performing signed and unsigned scalar and vector multiplication is disclosed. The multiplier is configured to receive signed or unsigned multiplier and multiplicand operands in scalar or packed vector form. An effective sign for the multiplier and multiplicand operands may be calculated based upon each operand's most significant bit and a control signal. The effective signs may then be used to create and select a number of partial products according to Booth's algorithm. Once the partial products have been created and selected, they may be summed and the results may be output. The results may be signed or unsigned, and may represent vector or scalar quantities. When a vector multiplication is performed, the multiplier may be configured to generate and select partial products so as to effectively isolate the multiplication process for each pair of vector components.
    Type: Grant
    Filed: January 19, 2000
    Date of Patent: May 21, 2002
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Stuart F. Oberman, Ming Siu, Ravi Krishna Cherukuri
  • Publication number: 20010051969
    Abstract: A multimedia execution unit configured to perform vectored floating point and integer instructions. The execution unit may include an add/subtract pipeline having far and close data paths. The far path is configured to handle effective addition operations and effective subtraction operations for operands having an absolute exponent difference greater than one. The close path is configured to handle effective subtraction operations for operands having an absolute exponent difference less than or equal to one. The close path is configured to generate two output values, wherein one output value is the first input operand plus an inverted version of the second input operand, while the second output value is equal to the first output value plus one. Selection of the first or second output value in the close path effectuates the round-to-nearest operation for the output of the adder.
    Type: Application
    Filed: February 6, 2001
    Publication date: December 13, 2001
    Inventors: Stuart F. Oberman, Norbert Juffa, Fred Weber, Krishnan Ramani, Ravi Krishna Cherukuri
  • Patent number: 6298367
    Abstract: A multimedia execution unit configured to perform vectored floating point and integer instructions. The execution unit may include an add/subtract pipeline having far and close data paths. The far path is configured to handle effective addition operations and effective subtraction operations for operands having an absolute exponent difference greater than one. The close path is configured to handle effective subtraction operations for operands having an absolute exponent difference less than or equal to one. The close path is configured to generate two output values, wherein one output value is the first input operand plus an inverted version of the second input operand, while the second output value is equal to the first output value plus one. Selection of the first or second output value in the close path effectuates the round-to-nearest operation for the output of the adder.
    Type: Grant
    Filed: April 6, 1998
    Date of Patent: October 2, 2001
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Stuart F. Oberman, Norbert Juffa, Fred Weber, Krishnan Ramani, Ravi Krishna
  • Patent number: 6161173
    Abstract: A superscalar processor includes a central scheduler for multiple execution units. The scheduler presumes operations issued to a particular execution unit all have the same latency, e.g., one clock cycle, even though some of the operations have longer latencies, e.g., two clock cycles. The execution unit that executes the operations having with longer than expected latencies, includes scheduling circuitry that holds up particular operation pipelines when operands required for the pipelines will not be valid when the scheduler presumes. Accordingly, the design of the scheduler can be simplified and can accommodate longer latency operations without being significantly redesigned for the longer latency operations.
    Type: Grant
    Filed: May 7, 1999
    Date of Patent: December 12, 2000
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Ravi Krishna, Amos Ben-Meir, John G. Favor