Abstract: A deep trench capacitor structure including an SOI substrate comprising an SOI layer, a rare earth oxide layer, and a bulk substrate, the rare earth oxide layer is located below the SOI layer and above the bulk substrate, and the rare earth oxide layer insulates the SOI layer from the bulk substrate, and a deep trench capacitor extending from a top surface of the SOI layer, through the rare earth oxide layer, down to a location within the bulk substrate, the rare earth oxide layer contacts the deep trench capacitor at an interface between the rare earth oxide layer and the bulk substrate forming an incline away from the deep trench capacitor.

Abstract: In a vertical dynamic memory cell, monocrystalline semiconductor material of improved quality is provided for the channel of an access transistor by lateral epitaxial growth over an insulator material (which complements the capacitor dielectric in completely surrounding the storage node except at a contact connection structure, preferably of metal, from the access transistor to the storage node electrode) and etching away a region of the lateral epitaxial growth including a location where crystal lattice dislocations are most likely to occur; both of which features serve to reduce or avoid leakage of charge from the storage node. An isolation structure can be provided in the etched region such that space is provided for connections to various portions of a memory cell array.

Abstract: A dielectric mandrel structure is formed on a single crystalline semiconductor layer. An amorphous semiconductor material layer is deposited on the physically exposed surfaces of the single crystalline semiconductor layer and surfaces of the mandrel structure. Optionally, the amorphous semiconductor material layer can be implanted with at least one different semiconductor material. Solid phase epitaxy is performed on the amorphous semiconductor material layer employing the single crystalline semiconductor layer as a seed layer, thereby forming an epitaxial semiconductor material layer with uniform thickness. Remaining portions of the epitaxial semiconductor material layer are single crystalline semiconductor fins and thickness of these fins are sublithographic. After removal of the dielectric mandrel structure, the single crystalline semiconductor fins can be employed to form a semiconductor device.

Abstract: A dielectric template layer is deposited on a substrate. Line trenches are formed within the dielectric template layer by an anisotropic etch that employs a patterned mask layer. The patterned mask layer can be a patterned photoresist layer, or a patterned hard mask layer that is formed by other image transfer methods. A lower portion of each line trench is filled with an epitaxial rare-earth oxide material by a selective rare-earth oxide epitaxy process. An upper portion of each line trench is filled with an epitaxial semiconductor material by a selective semiconductor epitaxy process. The dielectric template layer is recessed to form a dielectric material layer that provides lateral electrical isolation among fin structures, each of which includes a stack of a rare-earth oxide fin portion and a semiconductor fin portion.

Abstract: A node dielectric and a conductive trench fill region filling a deep trench are recessed to a depth that is substantially coplanar with a top surface of a semiconductor-on-insulator (SOI) layer. A shallow trench isolation portion is formed on one side of an upper portion of the deep trench, while the other side of the upper portion of the deep trench provides an exposed surface of a semiconductor material of the conductive fill region. A selective epitaxy process is performed to deposit a raised source region and a raised strap region. The raised source region is formed directly on a planar source region within the SOI layer, and the raised strap region is formed directly on the conductive fill region. The raised strap region contacts the raised source region to provide an electrically conductive path between the planar source region and the conductive fill region.

Abstract: A memory device is provided including a semiconductor on insulator (SOI) substrate including a first semiconductor layer atop a buried dielectric layer, wherein the buried dielectric layer is overlying a second semiconductor layer. A capacitor is present in a trench, wherein the trench extends from an upper surface of the first semiconductor layer through the buried dielectric layer and extends into the second semiconductor layer. A protective oxide is present in a void that lies adjacent the first semiconductor layer, and a pass transistor is present atop the semiconductor on insulator substrate in electrical communication with the capacitor.

Abstract: After formation of a gate stack, regions in which a source and a drain are to be formed are recessed through the top semiconductor layer and into an upper portion of a buried single crystalline rare earth oxide layer of a semiconductor-on-insulator (SOI) substrate so that a source trench and drain trench are formed. An embedded single crystalline semiconductor portion epitaxially aligned to the buried single crystalline rare earth oxide layer is formed in each of the source trench and the drain trench to form a recessed source and a recessed drain, respectively. Protrusion of the recessed source and recessed drain above the bottom surface of a gate dielectric can be minimized to reduce parasitic capacitive coupling with a gate electrode, while providing low source resistance and drain resistance through the increased thickness of the recessed source and recessed drain relative to the thickness of the top semiconductor layer.

Abstract: A method of forming a deep trench capacitor in a semiconductor-on-insulator substrate is provided. The method may include providing a pad layer positioned above a bulk substrate, etching a deep trench into the pad layer and the bulk substrate extending from a top surface of the pad layer down to a location within the bulk substrate, and doping a portion of the bulk substrate to form a buried plate. The method further including depositing a node dielectric, an inner electrode, and a dielectric cap substantially filling the deep trench, the node dielectric being located between the buried plate and the inner electrode, the dielectric cap being located at a top of the deep trench, removing the pad layer, growing an insulator layer on top of the bulk substrate, and growing a semiconductor-on-insulator layer on top of the insulator layer.

Abstract: An improved semiconductor capacitor and method of fabrication is disclosed. A MIM stack, comprising alternating first-type and second-type metal layers (each separated by dielectric) is formed in a deep cavity. The entire stack can be planarized, and then patterned to expose a first area, and selectively etched to recess all first metal layers within the first area. A second selective etch is performed to recess all second metal layers within a second area. The etched recesses can be backfilled with dielectric. Separate electrodes can be formed; a first electrode formed in said first area and contacting all of said second-type metal layers and none of said first-type metal layers, and a second electrode formed in said second area and contacting all of said first-type metal layers and none of said second-type metal layers.

Abstract: An improved semiconductor capacitor and method of fabrication is disclosed. A MIM stack, comprising alternating first-type and second-type metal layers (each separated by dielectric) is formed in a deep cavity. The entire stack can be planarized, and then patterned to expose a first area, and selectively etched to recess all first metal layers within the first area. A second selective etch is performed to recess all second metal layers within a second area. The etched recesses can be backfilled with dielectric. Separate electrodes can be formed; a first electrode formed in said first area and contacting all of said second-type metal layers and none of said first-type metal layers, and a second electrode formed in said second area and contacting all of said first-type metal layers and none of said second-type metal layers.

Abstract: A dielectric template layer is deposited on a substrate. Line trenches are formed within the dielectric template layer by an anisotropic etch that employs a patterned mask layer. The patterned mask layer can be a patterned photoresist layer, or a patterned hard mask layer that is formed by other image transfer methods. A lower portion of each line trench is filled with an epitaxial rare-earth oxide material by a selective rare-earth oxide epitaxy process. An upper portion of each line trench is filled with an epitaxial semiconductor material by a selective semiconductor epitaxy process. The dielectric template layer is recessed to form a dielectric material layer that provides lateral electrical isolation among fin structures, each of which includes a stack of a rare-earth oxide fin portion and a semiconductor fin portion.

Abstract: Two trenches having different widths are formed in a semiconductor-on-insulator (SOI) substrate. An oxygen-impermeable layer and a fill material layer are formed in the trenches. The fill material layer and the oxygen-impermeable layer are removed from within a first trench. A thermal oxidation is performed to convert semiconductor materials underneath sidewalls of the first trench into an upper thermal oxide portion and a lower thermal oxide portion, while the remaining oxygen-impermeable layer on sidewalls of a second trench prevents oxidation of the semiconductor materials. After formation of a node dielectric on sidewalls of the second trench, a conductive material is deposited to fill the trenches, thereby forming a conductive trench fill portion and an inner electrode, respectively. The upper and lower thermal oxide portions function as components of dielectric material portions that electrically isolate two device regions.

Abstract: A semiconductor structure is provided that includes a semiconductor oxide layer having features. The semiconductor oxide layer having the features is located between an active semiconductor layer and a handle substrate. The semiconductor structure includes a planarized top surface of the active semiconductor layer such that the semiconductor oxide layer is beneath the planarized top surface. The features within the semiconductor oxide layer are mated with a surface of the active semiconductor layer.

Abstract: A high-k dielectric metal trench capacitor and improved isolation and methods of manufacturing the same is provided. The method includes forming at least one deep trench in a substrate, and filling the deep trench with sacrificial fill material and a poly material. The method further includes continuing with CMOS processes, comprising forming at least one transistor and back end of line (BEOL) layer. The method further includes removing the sacrificial fill material from the deep trenches to expose sidewalls, and forming a capacitor plate on the exposed sidewalls of the deep trench. The method further includes lining the capacitor plate with a high-k dielectric material and filling remaining portions of the deep trench with a metal material, over the high-k dielectric material. The method further includes providing a passivation layer on the deep trench filled with the metal material and the high-k dielectric material.

Abstract: A method of forming a deep trench capacitor includes providing a wafer. Devices are formed on a front side of the wafer. A through-silicon-via is formed on a substrate of the wafer. Deep trenches are formed on a back side of the wafer. A deep trench capacitor is formed in the deep trench. The through-silicon-via connects the deep trench capacitor to the devices.

Abstract: A dielectric template layer is deposited on a substrate. Line trenches are formed within the dielectric template layer by an anisotropic etch that employs a patterned mask layer. The patterned mask layer can be a patterned photoresist layer, or a patterned hard mask layer that is formed by other image transfer methods. A lower portion of each line trench is filled with an epitaxial rare-earth oxide material by a selective rare-earth oxide epitaxy process. An upper portion of each line trench is filled with an epitaxial semiconductor material by a selective semiconductor epitaxy process. The dielectric template layer is recessed to form a dielectric material layer that provides lateral electrical isolation among fin structures, each of which includes a stack of a rare-earth oxide fin portion and a semiconductor fin portion.

Abstract: A high-k dielectric metal trench capacitor and improved isolation and methods of manufacturing the same is provided. The method includes forming at least one deep trench in a substrate, and filling the deep trench with sacrificial fill material and a poly material. The method further includes continuing with CMOS processes, comprising forming at least one transistor and back end of line (BEOL) layer. The method further includes removing the sacrificial fill material from the deep trenches to expose sidewalls, and forming a capacitor plate on the exposed sidewalls of the deep trench. The method further includes lining the capacitor plate with a high-k dielectric material and filling remaining portions of the deep trench with a metal material, over the high-k dielectric material. The method further includes providing a passivation layer on the deep trench filled with the metal material and the high-k dielectric material.

Abstract: Deep trench capacitor structures and methods of manufacture are disclosed. The method includes forming a deep trench structure in a wafer including a substrate, buried oxide layer (BOX) and silicon (SOI) film. The structure includes a wafer including a substrate, buried insulator layer and a layer of silicon on insulator layer (SOI) having a single crystalline structure throughout the layer. The structure further includes a first plate in the substrate and an insulator layer in direct contact with the first plate. A doped polysilicon is in direct contact with the insulator layer and also in direct contact with the single crystalline structure of the SOI.

Abstract: A structure and method to fabricate a body contact on a transistor is disclosed. The method comprises forming a semiconductor structure with a transistor on a handle wafer. The structure is then inverted, and the handle wafer is removed. A silicided body contact is then formed on the transistor in the inverted position. The body contact may be connected to neighboring vias to connect the body contact to other structures or levels to form an integrated circuit.

Abstract: In a vertical dynamic memory cell, monocrystalline semiconductor material of improved quality is provided for the channel of an access transistor by lateral epitaxial growth over an insulator material (which complements the capacitor dielectric in completely surrounding the storage node except at a contact connection structure, preferably of metal, from the access transistor to the storage node electrode) and etching away a region of the lateral epitaxial growth including a location where crystal lattice dislocations are most likely to occur; both of which features serve to reduce or avoid leakage of charge from the storage node. An isolation structure can be provided in the etched region such that space is provided for connections to various portions of a memory cell array.