Patents by Inventor Ravi Nalla

Ravi Nalla has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9929097
    Abstract: In some embodiments, an improved mechanical adhesion of copper metallization to dielectric with partially cured epoxy fillers is presented. In this regard, a substrate build-up film is introduced having epoxy material and a plurality of epoxy microspheres, wherein an interior of the microspheres is not fully cured. Other embodiments are also disclosed and claimed.
    Type: Grant
    Filed: May 22, 2015
    Date of Patent: March 27, 2018
    Assignee: Intel Corporation
    Inventors: Ravi Nalla, Omar Bchir, Houssam Jomaa
  • Publication number: 20170276897
    Abstract: Technologies described herein provide an enhanced lens assembly. In some configurations, a lens assembly includes a barrel configured with a number of components arranged therein. The components include at least a first lens, a second lens and a spacer positioned between the lenses. At least one lens is fastened to the barrel by one or more techniques, which may include the application of an adhesive to hold the lens in a predetermined location within the barrel. In other techniques, a lens is fastened to the barrel by the use of a laser or other like device configured to weld the lens to the barrel. In some configurations, the first lens and the second lens can be separated by a spacer that is made from a material having a linear thermal expansion coefficient within a predetermined range.
    Type: Application
    Filed: March 25, 2016
    Publication date: September 28, 2017
    Inventors: Ravi Nalla, Pierre Henri Rene Della nave, Kevin James Matherson
  • Patent number: 9726962
    Abstract: The techniques disclosed herein provide an enhanced mount for a camera module. The mount comprises at least a first side and a second side. The sides are formed to enable contact with at least a portion of the camera module. The sides are configured with openings to enable a fastening material, such as an adhesive, to secure the camera module to the mount. Openings within the mount enable the use of a fastening material to secure the camera module to at least one surface of the mount while allowing the camera module and at least one surface to maintain the mechanical contact. In some configurations, one or more openings are formed such that a contraction of the fastening material pulls the camera module toward at least one surface of the mount.
    Type: Grant
    Filed: April 29, 2016
    Date of Patent: August 8, 2017
    Assignee: MICROSOFT TECHNOLOGY LICENSING, LLC
    Inventors: Ravi Nalla, Michael Nikkhoo, Igor Markovsky
  • Publication number: 20160079174
    Abstract: In some embodiments, an improved mechanical adhesion of copper metallization to dielectric with partially cured epoxy fillers is presented. In this regard, a substrate build-up film is introduced having epoxy material and a plurality of epoxy microspheres, wherein an interior of the microspheres is not fully cured. Other embodiments are also disclosed and claimed.
    Type: Application
    Filed: May 22, 2015
    Publication date: March 17, 2016
    Inventors: Ravi Nalla, Omar Bchir, Houssam Jomaa
  • Patent number: 9040842
    Abstract: In some embodiments, an improved mechanical adhesion of copper metallization to dielectric with partially cured epoxy fillers is presented. In this regard, a substrate build-up film is introduced having epoxy material and a plurality of epoxy microspheres, wherein an interior of the microspheres is not fully cured. Other embodiments are also disclosed and claimed.
    Type: Grant
    Filed: April 22, 2013
    Date of Patent: May 26, 2015
    Assignee: Intel Corporation
    Inventors: Ravi Nalla, Omar Bchir, Houssam Jomaa
  • Patent number: 8772924
    Abstract: Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods may include attaching a die to a carrier material, forming dielectric material surrounding the die, forming buildup layers in the dielectric material to form a coreless bumpless buildup package structure, and patterning the carrier material to form microchannel structures on the package structure.
    Type: Grant
    Filed: March 28, 2013
    Date of Patent: July 8, 2014
    Assignee: Intel Corporation
    Inventors: Ravi Nalla, Mathew J. Manusharow
  • Publication number: 20130299226
    Abstract: In some embodiments, an improved mechanical adhesion of copper metallization to dielectric with partially cured epoxy fillers is presented. In this regard, a substrate build-up film is introduced having epoxy material and a plurality of epoxy microspheres, wherein an interior of the microspheres is not fully cured. Other embodiments are also disclosed and claimed.
    Type: Application
    Filed: April 22, 2013
    Publication date: November 14, 2013
    Inventors: Ravi Nalla, Omar Bchir, Houssam Jomaa
  • Publication number: 20130214403
    Abstract: Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods may include attaching a die to a carrier material, forming dielectric material surrounding the die, forming buildup layers in the dielectric material to form a coreless bumpless buildup package structure, and patterning the carrier material to form microchannel structures on the package structure.
    Type: Application
    Filed: March 28, 2013
    Publication date: August 22, 2013
    Inventors: Ravi Nalla, Mathew J. Manusharow
  • Patent number: 8425785
    Abstract: In some embodiments, an improved mechanical adhesion of copper metallization to dielectric with partially cured epoxy fillers is presented. In this regard, a substrate build-up film is introduced having epoxy material and a plurality of epoxy microspheres, wherein an interior of the microspheres is not fully cured. Other embodiments are also disclosed and claimed.
    Type: Grant
    Filed: March 31, 2008
    Date of Patent: April 23, 2013
    Assignee: Intel Corporation
    Inventors: Ravi Nalla, Omar Bchir, Houssain Jomas
  • Patent number: 8252677
    Abstract: A method of forming solder bumps on a substrate is disclosed. The method includes forming a plurality of contact points on the substrate. The method further includes depositing a layer of surface finish material on the plurality of contact points. Furthermore, the method includes disposing a plurality of solder balls on the layer of surface finish material. Each solder ball of the plurality of solder balls has conductive material including a solder alloy and Phosphorus. Thereafter, the method includes applying a solder reflow process to the plurality of solder balls to configure a plurality of solder bumps on the substrate layer. The concentration of the Phosphorus in the solder material is based on target performance characteristic of the substrate having the plurality of solder bumps.
    Type: Grant
    Filed: September 28, 2007
    Date of Patent: August 28, 2012
    Assignee: Intel Corporation
    Inventors: Omar Bchir, Ravi Nalla
  • Patent number: 7985622
    Abstract: A method of forming collapse chip connection bumps on a semiconductor substrate is provided. The method includes providing a semiconductor substrate having a plurality of bump vias on a top surface of the semiconductor substrate and electroplating the plurality of bump vias to form a plurality of via pads on the top surface of the semiconductor substrate. The method also includes disposing a plurality of solder microballs on the top surface of the semiconductor substrate, wherein each solder microball is placed on a corresponding via pad on the semiconductor substrate and reflowing the plurality of solder microballs to form the collapse chip connection bumps on the semiconductor substrate.
    Type: Grant
    Filed: August 20, 2008
    Date of Patent: July 26, 2011
    Assignee: Intel Corporation
    Inventors: Ravi Nalla, Islam Salama, Charan Gurumurthy, Hamid Azimi
  • Patent number: 7831115
    Abstract: Optical die structures and associated package substrates are generally described. In one example, an electronic device includes a package substrate having a package substrate core, a dielectric layer coupled with the package substrate core, and one or more input/output (I/O) optical fibers coupled with the package substrate core or coupled with the build-up dielectric layer, or combinations thereof, the one or more I/O optical fibers to guide I/O optical signals to and from the package substrate wherein the one or more I/O optical fibers allow both input and output optical signals to travel through the one or more I/O optical fibers.
    Type: Grant
    Filed: March 20, 2008
    Date of Patent: November 9, 2010
    Assignee: Intel Corporation
    Inventors: Omar Bchir, Islam Salama, Charan Gurumurthy, Houssam Jomaa, Ravi Nalla
  • Patent number: 7825022
    Abstract: An electronic package includes a substrate (110, 310, 510) and a solder resist layer (120, 320, 520) over the substrate. The solder resist layer has a plurality of solder resist openings (121, 321, 521) therein. The electronic package further includes a finish layer (130, 330, 535) in the solder resist openings, an electrically conducting layer (140, 440) in the solder resist openings over the finish layer, and a solder material (150, 810) in the solder resist openings over the electrically conducting layer. The electrically conducting layer electrically connects the solder resist openings in order to enable the electrokinetic deposition of the solder material.
    Type: Grant
    Filed: April 30, 2009
    Date of Patent: November 2, 2010
    Assignee: Intel Corporation
    Inventors: Ravi Nalla, Charavana Gurumurthy
  • Publication number: 20100044862
    Abstract: A method of forming collapse chip connection bumps on a semiconductor substrate is provided. The method includes providing a semiconductor substrate having a plurality of bump vias on a top surface of the semiconductor substrate and electroplating the plurality of bump vias to form a plurality of via pads on the top surface of the semiconductor substrate. The method also includes disposing a plurality of solder microballs on the top surface of the semiconductor substrate, wherein each solder microball is placed on a corresponding via pad on the semiconductor substrate and reflowing the plurality of solder microballs to form the collapse chip connection bumps on the semiconductor substrate.
    Type: Application
    Filed: August 20, 2008
    Publication date: February 25, 2010
    Inventors: Ravi Nalla, Islam Salama, Charan Gurumurthy, Hamid Azimi
  • Patent number: 7651021
    Abstract: Electronic devices and methods for fabricating electronic devices are described. One method includes providing a substrate with a plurality of bonding pads thereon, and providing a plurality of solder microballs, the microballs including a coating thereon. The method also includes flowing the solder microballs onto the substrate and positioning the solder microballs on the bonding pads. The method also includes heating the solder microballs to reflow and form a joint between the solder microballs and the bonding pads. Other embodiments are described and claimed.
    Type: Grant
    Filed: December 28, 2007
    Date of Patent: January 26, 2010
    Assignee: Intel Corporation
    Inventors: Lakshmi Supriya, Ravi Nalla
  • Publication number: 20090277866
    Abstract: An electronic package includes a substrate (110, 310, 510) and a solder resist layer (120, 320, 520) over the substrate. The solder resist layer has a plurality of solder resist openings (121, 321, 521) therein. The electronic package further includes a finish layer (130, 330, 535) in the solder resist openings, an electrically conducting layer (140, 440) in the solder resist openings over the finish layer, and a solder material (150, 810) in the solder resist openings over the electrically conducting layer. The electrically conducting layer electrically connects the solder resist openings in order to enable the electrokinetic deposition of the solder material.
    Type: Application
    Filed: April 30, 2009
    Publication date: November 12, 2009
    Inventors: RAVI NALLA, CHARAVANA GURUMURTHY
  • Publication number: 20090242109
    Abstract: In some embodiments, an improved mechanical adhesion of copper metallization to dielectric with partially cured epoxy fillers is presented. In this regard, a substrate build-up film is introduced having epoxy material and a plurality of epoxy microspheres, wherein an interior of the microspheres is not fully cured. Other embodiments are also disclosed and claimed.
    Type: Application
    Filed: March 31, 2008
    Publication date: October 1, 2009
    Inventors: Ravi Nalla, Omar Behir, Houssain Jomas
  • Publication number: 20090238233
    Abstract: Optical die structures and associated package substrates are generally described. In one example, an electronic device includes a package substrate having a package substrate core, a dielectric layer coupled with the package substrate core, and one or more input/output (I/O) optical fibers coupled with the package substrate core or coupled with the build-up dielectric layer, or combinations thereof, the one or more I/O optical fibers to guide I/O optical signals to and from the package substrate wherein the one or more I/O optical fibers allow both input and output optical signals to travel through the one or more I/O optical fibers.
    Type: Application
    Filed: March 20, 2008
    Publication date: September 24, 2009
    Inventors: Omar Bchir, Islam Salama, Charan Gurumurthy, Houssam Jomaa, Ravi Nalla
  • Publication number: 20090238516
    Abstract: Package substrates for optical die structures are generally described. In one example, an apparatus includes a package substrate having one or more plated through hole (PTH) structures, an optical waveguide coupled with the package substrate, the optical waveguide having one or more input/output (I/O) optical signal pathways to route I/O signals to and from the package substrate, and one or more optical fibers coupled with the optical waveguide, the one or more optical fibers being disposed in the PTH structures to route I/O signals to and from a motherboard.
    Type: Application
    Filed: March 20, 2008
    Publication date: September 24, 2009
    Inventors: Omar J. Bchir, Islam Salama, Charan Gurumurthy, Houssam Jomaa, Ravi Nalla, Yonggang Li
  • Patent number: 7583871
    Abstract: Package substrates for optical die structures are generally described. In one example, an apparatus includes a package substrate having one or more plated through hole (PTH) structures, an optical waveguide coupled with the package substrate, the optical waveguide having one or more input/output (I/O) optical signal pathways to route I/O signals to and from the package substrate, and one or more optical fibers coupled with the optical waveguide, the one or more optical fibers being disposed in the PTH structures to route I/O signals to and from a motherboard.
    Type: Grant
    Filed: March 20, 2008
    Date of Patent: September 1, 2009
    Inventors: Omar J. Bchir, Islam Salama, Charan Gurumurthy, Houssam Jomaa, Ravi Nalla, Yonggang Li