Patents by Inventor Ravi Pillarisetty

Ravi Pillarisetty has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10850977
    Abstract: Techniques are disclosed for forming group III material-nitride (III-N) microelectromechanical systems (MEMS) structures on a group IV substrate, such as a silicon, silicon germanium, or germanium substrate. In some cases, the techniques include forming a III-N layer on the substrate and optionally on shallow trench isolation (STI) material, and then releasing the III-N layer by etching to form a free portion of the III-N layer suspended over the substrate. The techniques may include, for example, using a wet etch process that selectively etches the substrate and/or STI material, but does not etch the III-N material (or etches the III-N material at a substantially slower rate). Piezoresistive elements can be formed on the III-N layer to, for example, detect vibrations or deflection in the free/suspended portion of the III-N layer. Accordingly, MEMS sensors can be formed using the techniques, such as accelerometers, gyroscopes, and pressure sensors, for example.
    Type: Grant
    Filed: June 26, 2015
    Date of Patent: December 1, 2020
    Assignee: INTEL CORPORATION
    Inventors: Han Wui Then, Sansaptak Dasgupta, Sanaz K. Gardner, Ravi Pillarisetty, Marko Radosavljevic, Seung Hoon Sung, Robert S. Chau
  • Publication number: 20200373351
    Abstract: Embodiments of the present disclosure propose qubit substrates, as well as methods of fabricating thereof and related device assemblies. In one aspect of the present disclosure, a qubit substrate includes a base substrate of a doped semiconductor material, and a layer of a substantially intrinsic semiconductor material over the base substrate. Engineering a qubit substrate in this manner allows improving coherence times of qubits provided thereon, while, at the same time, being sufficiently mechanically robust so that it can be efficiently used in large-scale manufacturing.
    Type: Application
    Filed: September 18, 2017
    Publication date: November 26, 2020
    Applicant: Intel Corporation
    Inventors: Jeanette M. Roberts, Wesley T. Harrison, Adel A. Elsherbini, Stefano Pellerano, Zachary R. Yoscovits, Lester Lampert, Ravi Pillarisetty, Roman Caudillo, Hubert C. George, Nicole K. Thomas, David J. Michalak, Kanwaljit Singh, James S. Clarke
  • Patent number: 10847705
    Abstract: Embodiments of the present disclosure describe two approaches to providing flux bias line structures for superconducting qubit devices. The first approach, applicable to flux bias line structures that include at least one portion that terminates with a ground connection, resides in terminating such a portion with a ground connection that is electrically isolated from the common ground plane of a quantum circuit assembly. The second approach resides in providing a SQUID loop of a superconducting qubit device and a portion of the flux bias line structure over a portion of a substrate that is elevated with respect to other portions of the substrate. These approaches may be used or alone or in combination, and may improve grounding of and reduce crosstalk caused by flux bias lines in quantum circuit assemblies.
    Type: Grant
    Filed: February 15, 2018
    Date of Patent: November 24, 2020
    Assignee: Intel Corporation
    Inventors: Lester Lampert, Adel A. Elsherbini, James S. Clarke, Jeanette M. Roberts, Ravi Pillarisetty, David J. Michalak, Kanwaljit Singh, Roman Caudillo, Zachary R. Yoscovits, Nicole K. Thomas, Hubert C. George, Stefano Pellerano
  • Publication number: 20200365688
    Abstract: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a quantum well stack; an insulating material disposed above the quantum well stack, wherein the insulating material includes a trench; and a gate metal disposed on the insulating material and extending into the trench.
    Type: Application
    Filed: August 7, 2020
    Publication date: November 19, 2020
    Applicant: Intel Corporation
    Inventors: Hubert C. George, Ravi Pillarisetty, Jeanette M. Roberts, Nicole K. Thomas, James S. Clarke
  • Publication number: 20200365656
    Abstract: Disclosed herein are quantum dot devices and techniques. In some embodiments, a quantum computing processing device may include a quantum well stack, an array of quantum dot gate electrodes above the quantum well stack, and an associated array of selectors above the array of quantum dot gate electrodes. The array of quantum dot gate electrodes and the array of selectors may each be arranged in a grid.
    Type: Application
    Filed: September 28, 2017
    Publication date: November 19, 2020
    Applicant: Intel Corporation
    Inventors: Ravi Pillarisetty, Nicole K. Thomas, Abhishek A. Sharma, Hubert C. George, Jeanette M. Roberts, Zachary R. Yoscovits, Roman Caudillo, Kanwaljit Singh, James S. Clarke
  • Patent number: 10840431
    Abstract: An embodiment includes an apparatus comprising: a memory array comprising: a selector switch including top and bottom electrodes, a metal layer, and a solid electrolyte layer; a memory cell in series with the selector switch; bit and write lines, wherein (a) (i) the top electrode couples to one of the bit and write lines and the bottom electrode couples to another of the bit and write lines, and (a) (ii) the memory cell is between one of the top and bottom electrodes and one of the bit and write lines; wherein (b) (i) the metal layer includes silver (Ag), and (b) (ii) Ag ions from the metal layer form a conductive path in the SE layer when the top electrode is biased and disband the conductive path when the top electrode is not biased. Other embodiments Electrode are described herein.
    Type: Grant
    Filed: March 31, 2016
    Date of Patent: November 17, 2020
    Assignee: Intel Corporation
    Inventors: Elijah V. Karpov, Ravi Pillarisetty, Prashant Majhi, James S. Clarke, Uday Shah
  • Publication number: 20200357782
    Abstract: An embedded cross-point memory array is described. In an example, an integrated circuit structure includes a first die including a cross-point memory array comprising separate memory blocks, the memory blocks including orthogonally arranged conductive lines, and memory elements at cross-sections of the conductive lines. A first plurality of sockets is on the first die adjacent to the memory blocks, the first plurality of sockets comprising a first plurality of pads that connect to at least a portion to the conductive lines of the corresponding memory block. A second die includes logic circuitry and a second plurality of sockets comprising a second plurality of pads at least partially aligned with positions of the first plurality of pads on the first die. A top of the first die and a top of the second die face one another, wherein the first plurality of pads are bonded with the second plurality pads to directly connect the cross-point memory array to the logic circuitry.
    Type: Application
    Filed: September 25, 2017
    Publication date: November 12, 2020
    Inventors: Elijah V. KARPOV, Prashant MAJHI, Brian S. DOYLE, Ravi PILLARISETTY, Yih WANG
  • Publication number: 20200350423
    Abstract: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include a (111) silicon substrate, a (111) germanium quantum well layer above the substrate, and a plurality of gates above the quantum well layer. In some embodiments, a quantum dot device may include a silicon substrate, an insulating material above the silicon substrate, a quantum well layer above the insulating material, and a plurality of gates above the quantum well layer.
    Type: Application
    Filed: September 28, 2017
    Publication date: November 5, 2020
    Applicant: Intel Corporation
    Inventors: Ravi Pillarisetty, Van H. Le, Nicole K. Thomas, Hubert C. George, Jeanette Roberts, Payam Amin, Zachary R. Yoscovits, Roman Caudillo, James S. Clarke, Roza Kotlyar, Kanwaljit Singh
  • Patent number: 10825861
    Abstract: An embodiment includes an apparatus comprising: first and second electrodes; first and second insulation layers between the first and second electrodes; and a middle layer between the first and second insulation layers; wherein (a) the middle layer includes material that has a first resistance when the first electrode is biased at a first voltage level and a second resistance when the first electrode is biased at a second voltage level; (b) the first resistance is less than the second resistance and the first voltage level is greater than the second voltage level. Other embodiments are described herein.
    Type: Grant
    Filed: March 31, 2016
    Date of Patent: November 3, 2020
    Assignee: Intel Corporation
    Inventors: Elijah V. Karpov, Prashant Majhi, Ravi Pillarisetty, Uday Shah, James S. Clarke
  • Patent number: 10818799
    Abstract: Disclosed herein are vertical transistor devices and techniques. In some embodiments, a device may include: a semiconductor substrate; a first transistor in a first layer on the semiconductor substrate; and a second transistor in a second layer, wherein the second transistor includes a first source/drain (S/D) contact and a second S/D contact, the first layer is between the second layer and the semiconductor substrate, and the first S/D contact is between the second S/D contact and the first layer. In some embodiments, a device may include: a semiconductor substrate; and a transistor above the semiconductor substrate, wherein the transistor includes a channel and a source/drain (S/D) contact between the channel and the semiconductor substrate.
    Type: Grant
    Filed: December 24, 2016
    Date of Patent: October 27, 2020
    Assignee: Intel Corporation
    Inventors: Ravi Pillarisetty, Abhishek A. Sharma, Van H. Le, Gilbert W. Dewey, Willy Rachmady
  • Publication number: 20200335501
    Abstract: Multiple non-silicon semiconductor material layers may be stacked within a fin structure. The multiple non-silicon semiconductor material layers may include one or more layers that are suitable for P-type transistors. The multiple non-silicon semiconductor material layers may further include one or more one or more layers that are suited for N-type transistors. The multiple non-silicon semiconductor material layers may further include one or more intervening layers separating the N-type from the P-type layers. The intervening layers may be at least partially sacrificial, for example to allow one or more of a gate, source, or drain to wrap completely around a channel region of one or more of the N-type and P-type transistors.
    Type: Application
    Filed: March 2, 2018
    Publication date: October 22, 2020
    Applicant: Intel Corporation
    Inventors: Gilbert Dewey, Patrick Morrow, Ravi Pillarisetty, Rishabh Mehandru, Cheng-ying Huang, Willy Rachmady, Aaron Lilak
  • Patent number: 10811336
    Abstract: Electronic devices, memory devices, and computing devices are disclosed. An electronic device includes electronic circuitry, a temperature sensor, a heat sink, at least one thermoelectric material, a thermally conductive material configured to thermally couple the electronic circuitry to the at least one thermoelectric material, and a transistor. The temperature sensor is configured to monitor a temperature of the electronic circuitry. The transistor is configured to selectively enable thermoelectric current to flow through the at least one thermoelectric material and dissipate heat from the thermally conductive material to the heat sink responsive to fluctuations in the temperature of the electronic circuitry detected by the temperature sensor.
    Type: Grant
    Filed: April 30, 2018
    Date of Patent: October 20, 2020
    Assignee: Intel Corporation
    Inventors: Ravi Pillarisetty, Abhishek A. Sharma, Elijah V. Karpov, Prashant Majhi, Brian S. Doyle
  • Patent number: 10811461
    Abstract: Substrates, assemblies, and techniques for a transmission gate that includes an n-type back end transistor and a p-type back end transistor in parallel with the n-type back end transistor. The transmission gate can be on a non-silicon substrate and include a second gate, a p-type semiconducting layer over the second gate, an n-type semiconducting layer over the p-type semiconducting layer, a bit line over the n-type semiconducting layer, a first gate over the n-type semiconducting layer, and a source line over the n-type semiconducting layer. The transmission gate may be coupled to a memory element.
    Type: Grant
    Filed: December 30, 2016
    Date of Patent: October 20, 2020
    Assignee: Intel Corporation
    Inventors: Abhishek A. Sharma, Ravi Pillarisetty, Van H. Le, Gilbert W. Dewey
  • Patent number: 10804399
    Abstract: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a quantum well stack with first and second quantum well layers, a first set of gates disposed on the quantum well stack such that the first quantum well layer is disposed between the barrier layer and the first set of gates, a first set of conductive pathways extending from the first set of gates to a first face of the quantum dot device, a second set of gates disposed on the quantum well stack such that the second quantum well layer is disposed between the barrier layer and the second set of gates, and a second set of conductive pathways extending from the second set of gates to a second face of the quantum dot device, wherein the second face is different from the first face.
    Type: Grant
    Filed: September 24, 2016
    Date of Patent: October 13, 2020
    Assignee: Intel Corporation
    Inventors: Ravi Pillarisetty, Jeanette M. Roberts, Nicole K. Thomas, Hubert C. George, James S. Clarke
  • Patent number: 10803396
    Abstract: Disclosed herein are superconducting qubit devices with Josephson Junctions utilizing resistive switching materials, i.e., resistive Josephson Junctions (RJJs), as well as related methods and quantum circuit assemblies. In some embodiments, an RJJ may include a bottom electrode, a top electrode, and a resistive switching layer (RSL) disposed between the bottom electrode and the top electrode. Using the RSLs in Josephson Junctions of superconducting qubits may allow fine tuning of junction resistance, which is particularly advantageous for optimizing performance of superconducting qubit devices. In addition, RJJs may be fabricated using methods that could be efficiently used in large-scale manufacturing, providing a substantial improvement with respect to approaches for forming conventional Josephson Junctions, such as e.g. double-angle shadow evaporation approach.
    Type: Grant
    Filed: June 19, 2018
    Date of Patent: October 13, 2020
    Assignee: Intel Corporation
    Inventors: Zachary R. Yoscovits, Roman Caudillo, Ravi Pillarisetty, Hubert C. George, Adel A. Elsherbini, Lester Lampert, James S. Clarke, Nicole K. Thomas, Kanwaljit Singh, David J. Michalak, Jeanette M. Roberts
  • Publication number: 20200321395
    Abstract: Embedded non-volatile memory structures having an independently sized selector element and memory element are described. In an example, a memory device includes a metal layer. A selector element is above the metal layer. A memory element is above the metal line. A spacer surrounds one of the selector element and the memory element having a smallest width, and wherein the one of the selector element and the memory element not surrounded by the spacer has a width substantially identical to the spacer and is in alignment with the spacer.
    Type: Application
    Filed: September 29, 2017
    Publication date: October 8, 2020
    Inventors: Brian S. DOYLE, Abhishek A. SHARMA, Ravi PILLARISETTY, Elijah V. KARPOV, Prashant MAJHI
  • Publication number: 20200321436
    Abstract: Quantum dot devices, and related systems and methods, are disclosed herein. In some embodiments, a quantum dot device may include a quantum well stack; a plurality of first gates above the quantum well stack; and a plurality of second gates above the quantum well stack; wherein the plurality of first gates are arranged in electrically continuous first rows and the plurality of second gates are arranged in electrically continuous second rows parallel to the first rows. Quantum dot devices according to various embodiments of the present disclosure are based on arranging first and second gates in hexagonal/honeycomb arrays.
    Type: Application
    Filed: December 23, 2017
    Publication date: October 8, 2020
    Applicant: Intel Corporation
    Inventors: Ravi Pillarisetty, Hubert C. George, Nicole K. Thomas, Jeanette M. Roberts, Roman Caudillo, Zachary R. Yoscovits, Kanwaljit Singh, Roza Kotlyar, Patrick H. Keys, James S. Clarke
  • Publication number: 20200312846
    Abstract: An integrated circuit includes: a germanium-containing fin structure above a layer of insulation material; a group III-V semiconductor material containing fin structure above the layer of insulation material; a first gate structure on a portion of the germanium-containing fin structure; a second gate structure on a portion of the group III-V semiconductor material containing fin structure; a first S/D region above the layer of insulation material and laterally adjacent to the portion of the germanium-containing fin structure, the first S/D region comprising a p-type impurity and at least one of silicon or germanium; a second S/D region above the layer of insulation material and laterally adjacent to the portion of the group III-V semiconductor material containing fin structure, the second S/D region comprising an n-type impurity and a second group III-V semiconductor material; and a layer comprising germanium between the layer of insulation material and the second S/D region.
    Type: Application
    Filed: December 29, 2017
    Publication date: October 1, 2020
    Applicant: INTEL CORPORATION
    Inventors: Willy Rachmady, Abhishek A. Sharma, Ravi Pillarisetty, Patrick Morrow, Rishabh Mehandru, Aaron D. Lilak, Gilbert Dewey, Cheng-Ying Huang
  • Publication number: 20200312839
    Abstract: IC device including back-end-of-line (BEOL) transistors with crystalline channel material. A BEOL crystalline seed may be formed over a dielectric layer that has been planarized over a front-end-of-line (FEOL) transistor level that employs a monocrystalline substrate semiconductor. The BEOL crystalline seed may be epitaxial to the substrate semiconductor, or may have crystallinity independent of that of the substrate semiconductor. The BEOL crystalline seed may comprise a first material having a higher melt temperature than a melt material formed over the seed and over the dielectric layer. Through rapid melt growth, the melt material may be heated to a temperature sufficient to transition from an as-deposited state to a more crystalline state that is derived from, and therefore associated with, the BEOL crystalline seed. A BEOL transistor may then be fabricated from the crystallized material.
    Type: Application
    Filed: March 27, 2019
    Publication date: October 1, 2020
    Applicant: Intel Corporation
    Inventors: Prashant Majhi, Abhishek Sharma, Brian Doyle, Ravi Pillarisetty, Willy Rachmady
  • Publication number: 20200312963
    Abstract: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a quantum well stack and a plurality of linear arrays of gates above the quantum well stack to control quantum dot formation in the quantum well stack. An insulating material may be between a first linear array of gates and a second linear array of gates, the insulating material may be between individual gates in the first linear array of gates, and gate metal of the first linear array of gates may extend over the insulating material.
    Type: Application
    Filed: March 27, 2019
    Publication date: October 1, 2020
    Applicant: Intel Corporation
    Inventors: Stephanie A. Bojarski, Hubert C. George, Sarah Atanasov, Nicole K. Thomas, Ravi Pillarisetty, Lester Lampert, Thomas Francis Watson, David J. Michalak, Roman Caudillo, Jeanette M. Roberts, James S. Clarke