Patents by Inventor Ravi Pillarisetty

Ravi Pillarisetty has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190312128
    Abstract: Disclosed herein are quantum dot device packages, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device package may include a die having a quantum dot device, wherein the quantum dot device includes a quantum well stack, gates disposed above the quantum well stack, and conductive pathways coupled between associated ones of the gates and conductive contacts of the die. The quantum dot device package may also include a package substrate, wherein conductive contacts are disposed on the package substrate, and first level interconnects are disposed between the die and the package substrate, coupling the conductive contacts of the die with associated conductive contacts of the package substrate.
    Type: Application
    Filed: June 8, 2016
    Publication date: October 10, 2019
    Applicant: Intel Corporation
    Inventors: Jeanette M. Roberts, Ravi Pillarisetty, David J. Michalak, Zachary R. Yoscovits, James S. Clarke, Adel A. Elsherbini
  • Patent number: 10439134
    Abstract: Techniques are disclosed for forming non-planar resistive memory cells, such as non-planar resistive random-access memory (ReRAM or RRAM) cells. The techniques can be used to reduce forming voltage requirements and/or resistances involved (such as the resistance during the low-resistance state) relative to planar resistive memory cells for a given memory cell space. The non-planar resistive memory cell includes a first electrode, a second electrode, and a switching layer disposed between the first and second electrodes. The second electrode may be substantially between opposing portions of the switching layer, and the first electrode may be substantially adjacent to at least two sides of the switching layer, after the non-planar resistive memory cell is formed. In some cases, an oxygen exchange layer (OEL) may be disposed between the switching layer and one of the first and second electrodes to, for example, increase flexibility in incorporating materials in the cell.
    Type: Grant
    Filed: March 25, 2014
    Date of Patent: October 8, 2019
    Assignee: INTEL CORPORATION
    Inventors: Prashant Majhi, Elijah V. Karpov, Uday Shah, Niloy Mukherjee, Charles C. Kuo, Ravi Pillarisetty, Brian S. Doyle, Robert S. Chau
  • Publication number: 20190304963
    Abstract: A backend electrostatic discharge (ESD) diode device structure is presented comprising: a first structure comprising a first material, wherein the first material includes metal; a second structure adjacent to the first structure, wherein the second structure comprises a second material, wherein the second material includes a semiconductor or an oxide; and a third structure adjacent to the second structure, wherein the third structure comprises of the first material, wherein the second structure is between the first and third structures. Other embodiments are also disclosed and claimed.
    Type: Application
    Filed: March 29, 2018
    Publication date: October 3, 2019
    Applicant: Intel Corporation
    Inventors: Prashant Majhi, Ilya Karpov, Brian Doyle, Ravi Pillarisetty, Abhishek Sharma
  • Publication number: 20190305045
    Abstract: An integrated circuit structure includes: a field-effect transistor including a semiconductor region including a semiconductor material having a bandgap less than or equal to that of silicon, a semiconductor source and a semiconductor drain, the semiconductor region being between the semiconductor source and the semiconductor drain, a gate electrode, a gate dielectric between the semiconductor region and the gate electrode, a source contact adjacent to the semiconductor source, and a drain contact adjacent to the semiconductor drain; and a resistive switch or a capacitor electrically connected to the drain contact. One of the source contact and the drain contact includes a threshold switching region, to be a selector for the resistive switch or the capacitor. In some embodiments, the threshold switching region includes a threshold switching oxide or a threshold switching chalcogenide, and the resistive switch or the capacitor is part of a resistive memory cell or capacitive memory cell.
    Type: Application
    Filed: March 30, 2018
    Publication date: October 3, 2019
    Applicant: INTEL CORPORATION
    Inventors: Abhishek A. Sharma, Brian S. Doyle, Ravi Pillarisetty, Prashant Majhi, Elijah V. Karpov
  • Publication number: 20190305121
    Abstract: Techniques and mechanisms for providing efficient transistor functionality of an integrated circuit. In an embodiment, a transistor device comprises a first body of a high mobility semiconductor and a second body of a wide bandgap semiconductor. The first body adjoins each of, and is disposed between, the second body and a gate dielectric layer of the transistor. The second body extends between, and variously adjoins, each of a source of the transistor and a drain of the transistor. A location of the second body mitigates current leakage that might otherwise occur via the first body. In another embodiment, a mobility of the first body is equal to or greater than 100 cm2/V·s, wherein a bandgap of the second body is equal to or greater than 2.0 eV.
    Type: Application
    Filed: March 28, 2018
    Publication date: October 3, 2019
    Applicant: Intel Corporation
    Inventors: Abhishek A. Sharma, Gilbert Dewey, Van H. Le, Willy Rachmady, Ravi Pillarisetty
  • Publication number: 20190305038
    Abstract: Described herein are structures that include interconnects for providing electrical connectivity in superconducting quantum circuits. One structure includes a first and a second interconnects provided over a surface of an interconnect support layer, e.g. a substrate, on which superconducting qubits are provided, a lower interconnect provided below such surface (i.e. below-plane interconnect), and vias for providing electrical interconnection between the lower interconnect and each of the first and second interconnects. Providing below-plane interconnects in superconducting quantum circuits allows realizing superconducting and mechanically stable interconnects. Implementing below-plane interconnects by bonding of two substrates, material for which could be selected, allows minimizing the amount of spurious two-level systems in the areas surrounding below-plane interconnects while allowing different choices of materials to be used. Methods for fabricating such structures are disclosed as well.
    Type: Application
    Filed: July 1, 2016
    Publication date: October 3, 2019
    Applicant: Intel Corporation
    Inventors: David J. Michalak, Ravi Pillarisetty, Zachary R. Yoscovits, Jeanette M. Roberts, James S. Clarke
  • Publication number: 20190305037
    Abstract: Described herein are structures that include interconnects for providing electrical connectivity in superconducting quantum circuits. In one aspect of the present disclosure, a structure includes a first and a second interconnects provided over a surface of an interconnect support layer on which superconducting qubits are provided (which could be a substrate), a lower interconnect provided below such surface, and vias for providing electrical interconnection between the lower interconnect and each of the first and second interconnects. The lower interconnect includes a material of the interconnect support layer doped to be superconductive. Providing below-plane interconnects in superconducting quantum circuits allows realizing superconducting and mechanically stable interconnects. Implementing below-plane interconnects by doping the interconnect support layer, material for which could be selected, allows minimizing the amount of spurious TLS's in the areas surrounding below-plane interconnects.
    Type: Application
    Filed: July 1, 2016
    Publication date: October 3, 2019
    Applicant: Intel Corporation
    Inventors: David J. Michalak, Jeanette M. Roberts, Ravi Pillarisetty, Zachary R. Yoscovits, James S. Clarke
  • Publication number: 20190304974
    Abstract: Techniques and mechanisms for providing a space efficient complementary metal-oxide-semiconductor (CMOS) circuit. In an embodiment, a p-type transistor of a circuit is to conduct current in a direction parallel to a surface of a semiconductor substrate, wherein an n-type thin film transistor (TFT) of the circuit is to conduct current in a direction which is orthogonal to the surface. A first interconnect is directly coupled to each of the two transistors, wherein the first interconnect, a high mobility channel structure of the n-type TFT, and a source or drain of the p-type transistor are on the same line of direction. A second interconnect comprises a conductive path which extends to respective gates of the p-type transistor and the n-type TFT, wherein the conductive path is limited to a region over a footprint of the p-type transistor. In another embodiment, functionality of a logical inverter is provided with the circuit.
    Type: Application
    Filed: March 30, 2018
    Publication date: October 3, 2019
    Applicant: Intel Corporation
    Inventors: Abhishek A. Sharma, Van H. Le, Gilbert Dewey, Willy Rachmady, Ravi Pillarisetty
  • Publication number: 20190296214
    Abstract: Described herein are structures that include Josephson Junctions (JJs) to be used in superconducting qubits of quantum circuits disposed on a substrate. The JJs of these structures are fabricated using an approach that can be efficiently used in large scale manufacturing, providing a substantial improvement with respect to conventional approaches which include fabrications steps which are not manufacturable. In one aspect of the present disclosure, the proposed approach includes providing a patterned superconductor layer over a substrate, providing a layer of surrounding dielectric over the patterned superconductor layer, and providing a via opening in the layer of surrounding dielectric over a first portion of the patterned superconductor layer. The proposed approach further includes depositing in the via opening a first superconductor, a barrier dielectric, and a second superconductor to form, respectively, a base electrode, a tunnel barrier layer, and a top electrode of the JJ.
    Type: Application
    Filed: June 13, 2016
    Publication date: September 26, 2019
    Applicant: Intel Corporation
    Inventors: Zachary R. YOSCOVITS, David J. MICHALAK, Jeanette M. ROBERTS, Ravi PILLARISETTY, James S. CLARKE
  • Publication number: 20190296081
    Abstract: Selector-based electronic devices, inverters, memory devices, and computing devices include a first selector and a second selector. The first selector and the second selector are electrically connected in series between a first voltage source terminal and a second voltage source terminal. The electronic device also includes a transistor electrically connected between an input terminal and a terminal between the first selector and the second selector.
    Type: Application
    Filed: March 23, 2018
    Publication date: September 26, 2019
    Applicant: INTEL CORPORATION
    Inventors: Abhishek A. Sharma, Brian S. Doyle, Ravi Pillarisetty, Prashant Majhi, Elijah V. Karpov
  • Publication number: 20190296104
    Abstract: A thin film transistor (TFT) apparatus is disclosed, where the apparatus includes a gate comprising metal, a source and a drain, a semiconductor body, and two or more dielectric structures between the gate and the semiconductor body. In an example, the two or more dielectric structures may include at least a first dielectric structure having a first bandgap and a second dielectric structure having a second bandgap. The first bandgap may be different from the second bandgap. The TFT apparatus may be a back-gated TFT apparatus where the source is at least in part coplanar with the drain, and the gate is non-coplanar with the source and the drain.
    Type: Application
    Filed: March 20, 2018
    Publication date: September 26, 2019
    Applicant: Intel Corporation
    Inventors: Abhishek A. Sharma, Willy Rachmady, Van H. Le, Gilbert Dewey, Ravi Pillarisetty
  • Patent number: 10424620
    Abstract: A non-volatile memory device is disclosed, in which a ballast resistor layer is disposed between the selector element and memory element of a given memory cell of the device. The material composition of the ballast resistor can be customized, as desired, and in some cases may be, for example, a sub-stoichiometric oxide of hafnium oxide (HfOx), tantalum oxide (TaOx), or titanium dioxide (TiOx), or an alloy of any thereof. In accordance with some embodiments, the integrated ballast resistor may serve the function of damping current surge related to the snapback characteristics of the selector element, preserving control of memory element switching. In accordance with some embodiments, an integrated ballast resistor layer provided as described herein may be implemented, for example, in any of a wide range of resistive random-access memory (RRAM) architectures and spin-transfer torque magnetic random-access memory (STTMRAM) architectures, including cross-point implementations of these types of architectures.
    Type: Grant
    Filed: December 23, 2015
    Date of Patent: September 24, 2019
    Assignee: INTEL CORPORATION
    Inventors: Prashant Majhi, Elijah V. Karpov, Ravi Pillarisetty, Uday Shah, Niloy Mukherjee
  • Publication number: 20190288176
    Abstract: Described herein are structures that include Josephson Junctions to be used in superconducting qubits of quantum circuits disposed on a substrate. In one aspect of the present disclosure, at least a part of a Josephson Junction of a superconducting qubit is suspended over a substrate, forming a gap between at least the portion of the Josephson Junction and the substrate. Moving at least a portion of the Josephson Junction further away from the substrate by suspending at least a part of the Junction over the substrate allows reducing spurious two-level systems present in the vicinity of the Junction, which, in turn, improves on the qubit decoherence problem. Methods for fabricating such structures are disclosed as well.
    Type: Application
    Filed: June 13, 2016
    Publication date: September 19, 2019
    Applicant: Intel Corporation
    Inventors: Zachary R. Yoscovits, David J. Michalak, Jeanette M. Roberts, Ravi Pillarisetty, James S. Clarke
  • Publication number: 20190287789
    Abstract: III-N semiconductor heterostructures including a raised III-N semiconductor structures with inclined sidewall facets are described. In embodiments, lateral epitaxial overgrowth favoring semi-polar inclined sidewall facets is employed to bend crystal defects from vertical propagation to horizontal propagation. In embodiments, arbitrarily large merged III-N semiconductor structures having low defect density surfaces may be overgrown from trenches exposing a (100) surface of a silicon substrate. III-N devices, such as III-N transistors, may be further formed on the raised III-N semiconductor structures while silicon-based transistors may be formed in other regions of the silicon substrate.
    Type: Application
    Filed: June 4, 2019
    Publication date: September 19, 2019
    Applicant: Intel Corporation
    Inventors: Sansaptak Dasgupta, Han Wui Then, Benjamin Chu-Kung, Marko Radosavljevic, Sanaz K. Gardner, Seung Hoon Sung, Ravi Pillarisetty, Robert S. Chau
  • Patent number: 10418487
    Abstract: A non-planar gate all-around device and method of fabrication thereby are described. In one embodiment, the device includes a substrate having a top surface with a first lattice constant. Embedded epi source and drain regions are formed on the top surface of the substrate. The embedded epi source and drain regions have a second lattice constant that is different from the first lattice constant. A channel nanowire having a third lattice is formed between and are coupled to the embedded epi source and drain regions. In an embodiment, the second lattice constant and the third lattice constant are different from the first lattice constant. A gate dielectric layer is formed on and all-around the channel nanowire. A gate electrode is formed on the gate dielectric layer and surrounding the channel nanowire.
    Type: Grant
    Filed: November 19, 2015
    Date of Patent: September 17, 2019
    Assignee: Intel Corporation
    Inventors: Willy Rachmady, Ravi Pillarisetty, Van H. Le, Jack T. Kavalieros, Robert S. Chau, Jessica S. Kachian
  • Publication number: 20190280047
    Abstract: Substrates, assemblies, and techniques for enabling a dual pedestal for resistive random access memory are disclosed herein. For example, in some embodiments, a device may include a substrate, wherein the substrate includes a fill metal, a first pedestal on the substrate, wherein the first pedestal is over the fill metal, and a second pedestal over the first pedestal, where the second pedestal is a bottom electrode for a memory cell. In an example, the first pedestal extends at least a length of the fill metal and the second pedestal extends less than a length of the first pedestal. In addition, the device can include a memory cell over the second pedestal.
    Type: Application
    Filed: September 30, 2016
    Publication date: September 12, 2019
    Applicant: Intel Corporation
    Inventors: Tejaswik K. Indukuri, Ravi Pillarisetty, Elijah V. Karpov, Satyarth Suri
  • Patent number: 10411122
    Abstract: Semiconductor devices having group III-V material active regions and graded gate dielectrics and methods of fabricating such devices are described. In an example, a semiconductor device includes a group III-V material channel region disposed above a substrate. A gate stack is disposed on the group III-V material channel region. The gate stack includes a graded high-k gate dielectric layer disposed directly between the III-V material channel region and a gate electrode. The graded high-k gate dielectric layer has a lower dielectric constant proximate the III-V material channel region and has a higher dielectric constant proximate the gate electrode. Source/drain regions are disposed on either side of the gate stack.
    Type: Grant
    Filed: August 23, 2018
    Date of Patent: September 10, 2019
    Assignee: Intel Corporation
    Inventors: Gilbert Dewey, Marko Radosavljevic, Ravi Pillarisetty, Matthew V. Metz
  • Publication number: 20190273197
    Abstract: One superconducting qubit device package disclosed herein includes a die having a first face and an opposing second face, and a package substrate having a first face and an opposing second face. The die includes a quantum device including a plurality of superconducting qubits and a plurality of resonators on the first face of the die, and a plurality of conductive pathways coupled between conductive contacts at the first face of the die and associated ones of the plurality of superconducting qubits or of the plurality of resonators. The second face of the package substrate also includes conductive contacts. The device package further includes first level interconnects disposed between the first face of the die and the second face of the package substrate, coupling the conductive contacts at the first face of the die with associated conductive contacts at the second face of the package substrate.
    Type: Application
    Filed: December 27, 2016
    Publication date: September 5, 2019
    Applicant: Intel Corporation
    Inventors: Jeanette M. Roberts, Adel A. Elsherbini, Shawna Liff, Johanna M. Swan, Roman Caudillo, Zachary R. Yoscovits, Nicole K. Thomas, Ravi Pillarisetty, Hubert C. George, James S. Clarke
  • Publication number: 20190266511
    Abstract: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include a base and a fin extending away from the base and including a quantum well layer. The device may further include a first gate disposed on a first side of the fin and a second gate disposed on a second side of the fin, different from the first side. Providing gates on different sides of a fin advantageously allows increasing the number of quantum dots which may be independently formed and manipulated in the fin. The quantum dots formed in such a device may be constrained in the x-direction by the one or more gates, in the y-direction by the fin, and in the z-direction by the quantum well layer, as discussed in detail herein. Methods for fabricating such devices are also disclosed.
    Type: Application
    Filed: September 27, 2016
    Publication date: August 29, 2019
    Applicant: Intel Corporation
    Inventors: Ravi Pillarisetty, Hubert C. George, Jeanette M. Roberts, Nicole K. Thomas, James S. Clarke
  • Publication number: 20190267692
    Abstract: Described herein are new transmission line structures for use as resonators and non-resonant interconnects in quantum circuits. In one aspect of the present disclosure, a proposed structure includes a substrate, a ground plane disposed over the substrate, a dielectric layer disposed over the ground plane, and a conductor strip disposed over the dielectric layer. In another aspect, a proposed structure includes a substrate, a lower ground plane disposed over the substrate, a lower dielectric layer disposed over the lower ground plane, a conductor strip disposed over the lower dielectric layer, an upper dielectric layer disposed over the conductor strip, and an upper ground plane disposed over the upper dielectric layer. Transmission line structures as proposed herein could be used for providing microwave connectivity to, from, or/and between the qubits, or to set the frequencies that address individual qubits. Methods for fabricating such structures are disclosed as well.
    Type: Application
    Filed: August 15, 2016
    Publication date: August 29, 2019
    Applicant: Intel Corporation
    Inventors: Jeanette M. Roberts, Ravi Pillarisetty, David J. Michalak, Zachary R. Yoscovits, James S. Clarke, Stefano Pellerano