Abstract: Integrated circuits including 3D memory structures are disclosed. Air-gaps are purposefully introduced between word lines. The word lines may be horizontal or vertical.

Abstract: A ferroelectric field-effect transistor (FeFET) includes first and second gate electrodes, source and drain regions, a semiconductor region between and physically connecting the source and drain regions, a first gate dielectric between the semiconductor region and the first gate electrode, and a second gate dielectric between the semiconductor region and the second gate electrode. The first gate dielectric includes a ferroelectric dielectric. In an embodiment, a memory cell includes this FeFET, with the first gate electrode being electrically connected to a wordline and the drain region being electrically connected to a bitline. In another embodiment, a memory array includes wordlines extending in a first direction, bitlines extending in a second direction, and a plurality of such memory cells at crossing regions of the wordlines and the bitlines. In each memory cell, the wordline is a corresponding one of the wordlines and the bitline is a corresponding one of the bitlines.

Abstract: Embodiments of the present disclosure describe a method of fabricating spin qubit device assemblies that utilize dopant-based spin qubits, i.e. spin qubit devices which operate by including a donor or an acceptor dopant atom in a semiconductor host layer. The method includes, first, providing a pair of gate electrodes over a semiconductor host layer, and then providing a window structure between the first and second gate electrodes, the window structure being a continuous solid material extending between the first and second electrodes and covering the semiconductor host layer except for an opening through which a dopant atom is to be implanted in the semiconductor host layer. By using a defined gate-first process, the method may address the scalability challenges and create a deterministic path for fabricating dopant-based spin qubits in desired locations, promoting wafer-scale integration of dopant-based spin qubit devices for use in quantum computing devices.

Abstract: A programmable array including a plurality cells aligned in a row on a substrate, wherein each of the plurality of cells includes a programmable element and a transistor, wherein the transistor includes a body including a first diffusion region and a second diffusion region on the first diffusion region and separated by a channel and the programmable element is disposed on the second diffusion region. A method of forming an integrated circuit including forming transistor bodies in a plurality rows on a substrate; forming a masking material as a plurality of rows across the bodies; etching the bodies through the masking material to define a width dimension of the transistor bodies; after etching the bodies, patterning each of the plurality of rows of the masking material into a plurality of individual masking units; and replacing each of the plurality of individual masking units with a programmable element.

Abstract: Strained thin film transistors are described. In an example, an integrated circuit structure includes a strain inducing layer on an insulator layer above a substrate. A polycrystalline channel material layer is on the strain inducing layer. A gate dielectric layer is on a first portion of the polycrystalline channel material. A gate electrode is on the gate dielectric layer, the gate electrode having a first side opposite a second side. A first conductive contact is adjacent the first side of the gate electrode, the first conductive contact on a second portion of the polycrystalline channel material. A second conductive contact adjacent the second side of the gate electrode, the second conductive contact on a third portion of the polycrystalline channel material.

Abstract: An apparatus is provided which comprises: a first transistor body comprising one or more semiconductor materials and having a length comprising a source region and a drain region with a channel region therebetween, a first dielectric layer over the first transistor body, a second transistor body comprising one or more semiconductor materials and having a length comprising a source region and a drain region with a channel region therebetween, wherein the second transistor body is over the first dielectric layer and wherein the length of the second transistor body is non-parallel to the length of the first transistor body, and a gate coupled with the channel regions of both the first transistor body and the second transistor body. Other embodiments are also disclosed and claimed.

Abstract: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a substrate and a quantum well stack disposed on the substrate. The quantum well stack may include a quantum well layer and a back gate, and the back gate may be disposed between the quantum well layer and the substrate.

Abstract: Thin film tunnel field effect transistors having relatively increased width are described. In an example, integrated circuit structure includes an insulator structure above a substrate. The insulator structure has a topography that varies along a plane parallel with a global plane of the substrate. A channel material layer is on the insulator structure. The channel material layer is conformal with the topography of the insulator structure. A gate electrode is over a channel portion of the channel material layer on the insulator structure. A first conductive contact is over a source portion of the channel material layer on the insulator structure, the source portion having a first conductivity type. A second conductive contact is over a drain portion of the channel material layer on the insulator structure, the drain portion having a second conductivity type opposite the first conductivity type.

Abstract: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a quantum well stack; a first gate above the quantum well stack, wherein the first gate includes a first gate metal and a first gate dielectric; and a second gate above the quantum well stack, wherein the second gate includes a second gate metal and a second gate dielectric, and the first gate is at least partially between a portion of the second gate and the quantum well stack.

Abstract: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include a base and a fin extending away from the base and including a quantum well layer. The device may further include a first gate disposed on a first side of the fin and a second gate disposed on a second side of the fin, different from the first side. Providing gates on different sides of a fin advantageously allows increasing the number of quantum dots which may be independently formed and manipulated in the fin. The quantum dots formed in such a device may be constrained in the x-direction by the one or more gates, in the y-direction by the fin, and in the z-direction by the quantum well layer, as discussed in detail herein. Methods for fabricating such devices are also disclosed.

Abstract: Disclosed herein are quantum dot devices with single electron transistor (SET) detectors. In some embodiments, a quantum dot device may include: a quantum dot formation region; a group of gates disposed on the quantum dot formation region, wherein the group of gates includes at least first, second, and third gates, spacers are disposed on sides of the first and second gates, wherein a first spacer is disposed on a side of the first gate proximate to the second gate, and a second spacer, physically separate from the first spacer, is disposed on a side of the second gate proximate to the first gate, and the third gate is disposed between the first and second gates and extends between the first and second spacers; and a SET disposed on the quantum dot formation region, proximate to the group of gates.

Abstract: Disclosed herein are quantum computing assemblies, as well as related computing devices and methods. For example, in some embodiments, a quantum computing assembly may include: a quantum device die to generate a plurality of qubits; a control circuitry die to control operation of the quantum device die; and a substrate; wherein the quantum device die and the control circuitry die are disposed on the substrate.

Abstract: Described herein are apparatuses, systems, and methods associated with metal-assisted transistors. A single crystal semiconductor material may be seeded from a metal. The single crystal semiconductor material may form a channel region, a source, region, and/or a drain region of the transistor. The metal may form the source contact or drain contact, and the source region, channel region, and drain region may be stacked vertically on the source contact or drain contact. Alternatively, a metal-assisted semiconductor growth process may be used to form a single crystal semiconductor material on a dielectric material adjacent to the metal. The portion of the semiconductor material on the dielectric material may be used to form the transistor. Other embodiments may be described and claimed.

Abstract: A 1S-1T ferroelectric memory cell is provided that include a transistor and a two-terminal selector device. The transistor exhibits a low conductive state and a high conductive state (channel resistance), depending on drive voltage. The two-terminal selector device exhibits one of an ON-state and an OFF-state depending upon whether the transistor is in its low conductive state or its high conductive state. The transistor may be, for instance, a ferroelectric gate vertical transistor. Modulation of a polarization state of ferroelectric material of the vertical transistor may be utilized to switch the state of the selector device. The memory cell may thus selectively be operated in one of an ON-state and an OFF-state depending upon whether the selector device is in its ON-state or OFF-state.

Abstract: A backend electrostatic discharge (ESD) diode device structure is presented comprising: a first structure comprising a first material, wherein the first material includes metal; a second structure adjacent to the first structure, wherein the second structure comprises a second material, wherein the second material includes a semiconductor or an oxide; and a third structure adjacent to the second structure, wherein the third structure comprises the first material, wherein the second structure is between the first and third structures.

Abstract: Embedded non-volatile memory structures having double selector elements are described. In an example, a memory device includes a word line. A double selector element is above the word line. The double selector element includes a first selector material layer, a second selector material layer different than the first selector material layer, and a conductive layer directly between the first selector material layer and the second selector material layer. A bipolar memory element is above the word line. A conductive electrode is between the double selector element and the bipolar memory element. A bit line is above the word line.

Abstract: A ferroelectric field-effect transistor (FeFET) includes first and second gate electrodes, source and drain regions, a semiconductor region between and physically connecting the source and drain regions, a first gate dielectric between the semiconductor region and the first gate electrode, and a second gate dielectric between the semiconductor region and the second gate electrode. The first gate dielectric includes a ferroelectric dielectric. In an embodiment, a memory cell includes this FeFET, with the first gate electrode being electrically connected to a wordline and the drain region being electrically connected to a bitline. In another embodiment, a memory array includes wordlines extending in a first direction, bitlines extending in a second direction, and a plurality of such memory cells at crossing regions of the wordlines and the bitlines. In each memory cell, the wordline is a corresponding one of the wordlines and the bitline is a corresponding one of the bitlines.

Abstract: A programmable array including a plurality cells aligned in a row on a substrate, wherein each of the plurality of cells includes a programmable element and a transistor, wherein the transistor includes a body including a first diffusion region and a second diffusion region on the first diffusion region and separated by a channel and the programmable element is disposed on the second diffusion region. A method of forming an integrated circuit including forming transistor bodies in a plurality rows on a substrate; forming a masking material as a plurality of rows across the bodies; etching the bodies through the masking material to define a width dimension of the transistor bodies; after etching the bodies, patterning each of the plurality of rows of the masking material into a plurality of individual masking units; and replacing each of the plurality of individual masking units with a programmable element.

Abstract: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include a base and a fin extending away from the base and including a quantum well layer. The device may further include a first gate disposed on a first side of the fin and a second gate disposed on a second side of the fin, different from the first side. Providing gates on different sides of a fin advantageously allows increasing the number of quantum dots which may be independently formed and manipulated in the fin. The quantum dots formed in such a device may be constrained in the x-direction by the one or more gates, in the y-direction by the fin, and in the z-direction by the quantum well layer, as discussed in detail herein. Methods for fabricating such devices are also disclosed.

Abstract: Disclosed herein are quantum dot devices with single electron transistor (SET) detectors. In some embodiments, a quantum dot device may include: a quantum dot formation region; a group of gates disposed on the quantum dot formation region, wherein the group of gates includes at least first, second, and third gates, spacers are disposed on sides of the first and second gates, wherein a first spacer is disposed on a side of the first gate proximate to the second gate, and a second spacer, physically separate from the first spacer, is disposed on a side of the second gate proximate to the first gate, and the third gate is disposed between the first and second gates and extends between the first and second spacers; and a SET disposed on the quantum dot formation region, proximate to the group of gates.