Abstract: Various aspects of the present disclosure generally relate to wireless communication. In some aspects, a user equipment (UE) may receive a first physical broadcast channel (PBCH) communication on a channel. The UE may decode the first PBCH communication as a decoded PBCH payload. The UE may reencode the decoded PBCH payload as a first pilot signal. The UE may receive a first data communication with first data. The UE may correct the channel for the first data based on the first pilot signal. The UE may decode the first data. Numerous other aspects are described.

Abstract: A data processing system comprises a pool of reconfigurable data flow resources and a runtime processor. The pool of reconfigurable data flow resources includes arrays of physical configurable units and memory. The runtime processor includes logic to receive a plurality of configuration files for user applications. The configuration files include configurations of virtual data flow resources required to execute the user applications. The runtime processor also includes logic to allocate physical configurable units and memory in the pool of reconfigurable data flow resources to the virtual data flow resources and load the configuration files to the allocated physical configurable units. The runtime processor further includes logic to execute the user applications using the allocated physical configurable units and memory.

Abstract: A system is presented that includes a communication link, a runtime processor coupled to the communication link, and a reconfigurable processor. The reconfigurable processor is adapted for generating an interrupt to the runtime processor in response to a predetermined event and includes multiple arrays of coarse-grained reconfigurable (CGR) units and an interface to the communication link that couples the reconfigurable processor to the runtime processor via the communication link. The runtime processor is adapted for configuring the interface to the communication link to provide access to the multiple arrays of coarse-grained reconfigurable units from a physical function driver and from at least one virtual function driver, and the reconfigurable processor is adapted for sending the interrupt to the physical function driver and to a virtual function driver of the at least one virtual function driver within the runtime processor.

Abstract: A data access method and apparatus for a heterogeneous processing system includes a host processor, a first processor coupled to a first memory, a second processor coupled to a second memory, and switch and bus circuitry that communicatively couples the host processor, the first processor, and the second processor. The host processor maps virtual addresses of the second memory to physical addresses of the switch and bus circuitry. The first processor is configured to directly access the second memory using the mapped physical addresses, and may be configured to directly access the second memory for reading and writing data while executing an application.

Abstract: Embodiments of the present disclosure include techniques for encoding and decoding metadata in error correction codes. During read operation, a decoder generates a first output corresponding to the at least one metadata bit having a first state and a second output corresponding to the at least one metadata bit having a second state. When one of the first and second outputs have a zero value, the decoder sets a value of the at least one metadata bit to the first state or the second state corresponding to the first output or the second output having the zero value. When both the first and second outputs are non-zero, the decoder decodes the codeword with the assumption of both the metadata bit having the first state and the second state to determine if the codeword is correctable with the at least one metadata bit.

Abstract: A system is presented that includes two data processing systems that are coupled via a network, each data processing system including a reconfigurable processor with a reconfigurable processor memory, a host that is coupled to the reconfigurable processor and that includes a host processor and a host memory that is coupled to the host processor, and a network interface controller (NIC) that is operatively coupled to the reconfigurable processor and to the host processor. The reconfigurable processor of one of the data processing systems is configured to implement a virtual function that uses a virtual address for a memory access operation. An application programming interface (API) in the host processor translates the virtual address into a physical address, and the NIC uses the physical address to initiate a direct memory access operation at the reconfigurable processor memory or the host memory of the other data processing system.

Abstract: Embodiments of the disclosure relate to an optical fiber cable. The optical fiber cable includes a subunit having a first interior surface and a first exterior surface. The first interior surface defines a central bore along a longitudinal axis of the optical fiber cable. At least one optical fiber is disposed within the central bore of the subunit, and a plurality of strengthening yarns is disposed around the subunit. A cable sheath disposed around the plurality of strengthening yarns. The cable sheath has a second interior surface and a second exterior surface. The second exterior surface defines an outermost surface of the optical fiber cable. The cable sheath includes from 55% to 68% by weight of a mineral-based flame retardant additive and from 35% to 45% by weight of a polymer blend. The polymer blend includes a co-polyester or co-polyether and a polyolefin or a polyolefin elastomer.

Abstract: A heterogeneous processing system including a host processor coupled to a host memory, a first processor coupled to a first memory, a second processor coupled to a second memory, multiple data transfer resources, and switch and bus circuitry that communicatively couples the host processor, the first processor, the second processor, and the data transfer resources. The host processor is configured to detect an application for execution by both the first processor and the second processor, to select one of multiple data transfer methods for transferring data between the first and second processors, and to configure the heterogeneous processing system based on the selected data transfer method. The data transfer methods include memory extension operation, one memory to memory transfer operation, and two memory to memory transfer operation using at least one intermediate host buffer.

Abstract: A heterogeneous processing system including a host processor, a first processor with a first memory and a first data transfer resource, a second processor with a second memory, and switch and bus circuitry that communicatively couples the processors and the data transfer resource. The host processor is programmed to map virtual addresses of the second memory to physical addresses of the switch and bus circuitry and to configure the first processor to perform one memory to memory transfer operation between the first and second memories using the data transfer resource. The first processor may be configured to program the first data transfer resource. A method including mapping virtual addresses of the second memory to physical addresses of the switch and bus circuitry, and configuring the first processor to perform one memory to memory transfer operation between the first and second memories using the first data transfer resource.

Abstract: Embodiments generally relate to improving reliability of processing cache lines with metadata symbols encoded into parity symbols of codewords. The data and metadata of a cache line are encoded into codewords where each codeword is a number of (1) message symbols, each including message bits from data of the cache line, and (2) parity symbols, each including parity bits determined from the message symbols and a metadata symbol. For each codeword of the cache line, the plurality of message and parity symbols are rotated so that a location of each symbol of one codeword is different from other codewords of the cache line. The codewords of the cache line are then stored in memory as rotated. In this manner, the reliability is improved by rotating symbols of the codewords of the cache line, with metadata symbols encoded into parity of codewords, before storage in memory.

Abstract: Embodiments generally relate to improving reliability of processing cache lines with metadata symbols encoded into parity symbols of codewords. The data and metadata of a cache line are encoded into codewords where each codeword is a number of (1) message symbols, each including message bits from data of the cache line, and (2) parity symbols, each including parity bits determined from the message symbols and a metadata symbol. For each codeword of the cache line, the plurality of message and parity symbols are rotated so that a location of each symbol of one codeword is different from other codewords of the cache line. The codewords of the cache line are then stored in memory as rotated. In this manner, the reliability is improved by rotating symbols of the codewords of the cache line, with metadata symbols encoded into parity of codewords, before storage in memory.

Abstract: A heterogeneous processing system and method including a host processor, a first processor coupled to a first memory, a second processor coupled to a second memory, and switch and bus circuitry that communicatively couples the host processor, the first processor, and the second processor. The host processor is programmed to map virtual addresses of the second memory to physical addresses of the switch and bus circuitry and to configure the first processor to directly access the second memory using the mapped physical addresses according to memory extension operation. The first processor may be a reconfigurable processor, a reconfigurable dataflow unit, or a compute engine. The first processor may directly read data from or directly write data to the second memory while executing an application. The method may include configuring the first processor to directly access the second memory while executing an application for reading or writing data.

Abstract: A test circuit is configured to test and calibrate an impedance of a driver of an integrated circuit. Testing the impedance includes driving first and second currents through the driver via a first contact pad and a ground metallization of the integrated circuit. Testing the impedance includes measuring the voltage at a test metalization while driving the first and second current while the test metalization is successively coupled to the first contact pad and the ground metallization while driving the first and second test currents.

Abstract: An integrated circuit includes an output pad, and I/O driver that drives data to the output pad, and a predriver that controls the I/O driver. The integrated circuit includes maximum voltage generator that receives a first supply voltage and a second supply voltage and outputs to the predriver a maximum voltage corresponding to the higher of the first supply voltage and the second supply voltage.

Abstract: Embodiments of the present disclosure include techniques for encoding and decoding metadata in error correction codes. During read operation, a decoder generates a first output corresponding to the at least one metadata bit having a first state and a second output corresponding to the at least one metadata bit having a second state. When one of the first and second outputs have a zero value, the decoder sets a value of the at least one metadata bit to the first state or the second state corresponding to the first output or the second output having the zero value. When both the first and second outputs are non-zero, the decoder decodes the codeword with the assumption of both the metadata bit having the first state and the second state to determine if the codeword is correctable with the at least one metadata bit.

Abstract: A data processing system including an array of reconfigurable units and a compiler configured to generate to execute a dataflow graph of a user application is disclosed. The dataflow graph includes a sequence of temporal partitions, each temporal partition including a sequence of graph control operations. Also disclosed is an intelligent graph orchestration and execution engine (IGOEE) configured to receive an optimization objective from the complier. The optimization objective can be for minimizing execution time of the reconfigurable processor or maximizing computing resource utilization of the reconfigurable processor. The IGOEE can reorganize the sequence of temporal partitions and the sequence of graph control operations within each temporal partition to satisfy the optimization objective; and execute the reorganized dataflow graph on the reconfigurable processor. A corresponding method is also disclosed herein.

Abstract: The disclosed technology relates to link-based resource allocation for a pool of reconfigurable processors. Resource allocation is provided for reconfigurable processors based on link bandwidths and link latencies. Runtime logic receives target link bandwidth and target link latency and rated link bandwidth and rated link latency. In response, the runtime logic allocates configuration files for an application, reconfigurable processors, and links between the processors. The runtime logic executes the allocated configuration files using the allocated processors and the allocated links. In another embodiment, the pool of reconfigurable processors comprise a cluster of processing nodes connected through a network.

Abstract: An integrated circuit includes an overvoltage protection circuit. The overvoltage protection circuit detects overvoltage events at a pad of the integrated circuit. The overvoltage protection circuit generates a max voltage signal that is the greater of the voltage at the pad and a supply voltage of the integrated circuit. The overvoltage protection circuit disables a PMOS transistor coupled to the pad by supplying the max voltage signal to the gate of the PMOS transistor when an overvoltage event is present at the pad.

Abstract: The present disclosure is directed to a voltage driver, where a combination of first and second resistance blocks controls a differential voltage swing on the outputs of the voltage driver. Variations of an input voltage are compensated by adding different values of the first resistance block to the second resistance block, while keeping a summation of the first and second resistance blocks at a constant value. Three different circuit diagrams are disclosed to generate these different resistances. In each circuit diagram, one or more control signals change the resistance of the combination of first and second resistance blocks. In some embodiments, the value of the second resistance block is changed by the first resistance block to maintain an impedance matching between a transmitter and a receiver, while changing of the first resistance block compensates for the differential voltage swing.

Abstract: The apparatus in some aspects may be a wireless device configured to operate a first transceiver in a first connected mode with a first radio access network (RAN) and a second transceiver in a second connected mode with a second RAN. The apparatus may further be configured to transmit a first communication via the first transceiver and obtain, based on a second communication via the second transceiver, an indication of a cancellation of one or more symbols for the first communication via the first transceiver. The apparatus may also be configured to refrain from transmitting, based on the indication, a remaining portion of the first communication via a set of symbols including the one or more symbols.