Patents by Inventor Ravinder Kumar

Ravinder Kumar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12684555
    Abstract: The apparatus in some aspects may be a wireless device configured to operate a first transceiver in a first connected mode with a first radio access network (RAN) and a second transceiver in a second connected mode with a second RAN. The apparatus may further be configured to transmit a first communication via the first transceiver and obtain, based on a second communication via the second transceiver, an indication of a cancellation of one or more symbols for the first communication via the first transceiver. The apparatus may also be configured to refrain from transmitting, based on the indication, a remaining portion of the first communication via a set of symbols including the one or more symbols.
    Type: Grant
    Filed: February 24, 2023
    Date of Patent: July 14, 2026
    Assignee: QUALCOMM Incorporated
    Inventors: Ravinder Kumar, Abbas Termos, Pak Yin Tam, Qiang Shen
  • Publication number: 20260197040
    Abstract: Various aspects generally relate to communication. In some aspects, a receiver may receive, from a transmitter over a wired infrastructure, a frequency division multiplexed (FDM) signal. The receiver may map the FDM signal to a spatial division multiplexed (SDM) signal including multiple spatial layers, wherein the SDM signal mapped to the FDM signal compensates for a frequency error between the transmitter and the receiver. The receiver may provide the SDM signal to a multiple-input multiple-output (MIMO) transceiver. Numerous other aspects are described.
    Type: Application
    Filed: January 7, 2026
    Publication date: July 9, 2026
    Inventors: Carl HARDIN, Rahul MALIK, Omar MEHANNA, Ravinder KUMAR
  • Publication number: 20260169712
    Abstract: A data processing system for selecting configurations for virtual functions includes a runtime processor coupled to a reconfigurable processor having arrays of coarse-grained reconfigurable units. The runtime processor receives a virtual function request specifying resource requirements including compute requirements, memory requirements, or performance requirements. The runtime processor analyzes the resource requirements to determine a resource profile characterizing the virtual function's computational needs, evaluates available configuration options that provide different array allocations, and selects a configuration that matches the resource profile to configuration capabilities. Selection is based on comparing the resource profile against capability thresholds, where configurations providing one array per virtual function satisfy low requirements, configurations providing two arrays satisfy medium requirements, and configurations providing four arrays satisfy high requirements.
    Type: Application
    Filed: February 5, 2026
    Publication date: June 18, 2026
    Applicant: SambaNova Systems, Inc.
    Inventors: Manish K. SHAH, Paul JORDAN, Maran WILSON, Ravinder KUMAR
  • Publication number: 20260169713
    Abstract: A system for allocating reconfigurable processor resources to virtual functions includes a runtime processor coupled to a multi-die reconfigurable processor via a communication link. The reconfigurable processor comprises first and second dies arranged in a package, each die having arrays of coarse-grained reconfigurable units. The runtime processor receives resource allocation requests for virtual functions, determines resource requirements for each virtual function including number of arrays and memory capacity, evaluates available resources across the first and second dies, and allocates arrays from the first die, the second die, or both dies to each virtual function based on the resource requirements and available resources. The runtime processor configures communication link interfaces to provide the allocated arrays to virtual function drivers, enabling efficient multi-tenant operation of the reconfigurable processor with optimized resource utilization and isolation between virtual functions.
    Type: Application
    Filed: February 5, 2026
    Publication date: June 18, 2026
    Applicant: SambaNova Systems, Inc.
    Inventors: Manish K. SHAH, Paul JORDAN, Maran WILSON, Ravinder KUMAR
  • Patent number: 12645497
    Abstract: A data processing system includes a runtime processor and a pool of reconfigurable data flow resources with memory units, busses, and arrays of physical configurable units. The runtime processor is operatively coupled to the pool of reconfigurable data flow resources and configured to load first and second configuration files for executing first and second user applications on first and second subsets of the arrays of physical configurable units and to assign first and second subsets of the memory units to the first and second user applications. The runtime processor starts execution of the first and second user applications on the first and second subsets of the arrays of physical configurable units, prevents the first user application from accessing the resources allocated to the second user application, and prevents the second user application from accessing resources allocated to the first user application.
    Type: Grant
    Filed: December 19, 2022
    Date of Patent: June 2, 2026
    Assignee: SambaNova Systems, Inc.
    Inventors: Ranen Chatterjee, Ravinder Kumar, Raghunath Shenbagam, Maran Wilson, Conrad Alexander Turlik, Arnav Goel, Arjun Sabnis, Yannan Chen
  • Patent number: 12608222
    Abstract: A data processing system is presented that is configured as a server in a client-server configuration for executing applications that a client in the client-server configuration can offload as execution tasks for execution on the server. The data processing system includes a reconfigurable processor, a storage device that stores configuration files for the applications, and a host processor that is coupled to the storage device and to the reconfigurable processor. The host processor is configured to receive an execution task of the execution tasks with an identifier of an application from the client, retrieve a configuration file that is associated with the application from the storage device using the identifier of the application, configure the reconfigurable processor with the configuration file, and start execution of the application on the reconfigurable processor, whereby the reconfigurable processor provides output data of the execution of the application to the client.
    Type: Grant
    Filed: April 12, 2023
    Date of Patent: April 21, 2026
    Assignee: SambaNova Systems, Inc
    Inventors: Arnav Goel, Ravinder Kumar, Qi Zheng, Milad Sharif, Jiayu Bai, Neal Sanghvi
  • Publication number: 20260095360
    Abstract: Methods, systems, and devices for wireless communications are described. Generally, the described techniques may enable a user equipment (UE) to use a frequency estimator (e.g., a maximum likelihood estimator) that may be based on a pilot signal sent over M distinct symbols. That is, the frequency estimator may be based on all available cross-correlations of pilot signals in a reference signal. In some examples, the frequency estimator may achieve an increased pull-in range and estimation performance based on weighting the available cross-correlations in accordance with the channel statistics. The described techniques may also support asymmetrical symbol spacings between pilot signals in one or more reference signals, which may further improve pull-in range of the frequency estimator. Additionally, or alternatively, aspects of the frequency estimator may be combined with aspects of another frequency estimator to increase the pull-in range with relatively low computation complexity at the UE.
    Type: Application
    Filed: September 26, 2025
    Publication date: April 2, 2026
    Inventors: Ravinder KUMAR, Paolo MINERO, Shamman NOOR SHOUDHA, Subramanya P.N. RAO, Jae Ho RYU, Yi HUANG
  • Patent number: 12572342
    Abstract: A data processing system is presented that includes a communication link, a runtime processor coupled to the communication link, and one or more reconfigurable processors. A reconfigurable processor of the one or more reconfigurable processors is adapted for generating an interrupt to the runtime processor in response to a predetermined event and includes arrays of coarse-grained reconfigurable (CGR) units and an interface to the communication link that couples the reconfigurable processor to the runtime processor via the communication link. The runtime processor is adapted for configuring the interface to the communication link to provide access to the arrays of CGR units through the communication link from a physical function driver and from a virtual function driver.
    Type: Grant
    Filed: February 1, 2023
    Date of Patent: March 10, 2026
    Assignee: SambaNova Systems, Inc.
    Inventors: Manish K. Shah, Paul Jordan, Maran Wilson, Ravinder Kumar
  • Publication number: 20260056913
    Abstract: A data processing system including an array of reconfigurable units and a compiler configured to generate to execute a dataflow graph of a user application is disclosed. The dataflow graph includes a sequence of temporal partitions, each temporal partition including a sequence of graph control operations. Also disclosed is an intelligent graph orchestration and execution engine (IGOEE) configured to receive an optimization objective from the complier. The IGOEE can reorganize the sequence of temporal partitions and the sequence of graph control operations within each temporal partition to satisfy the optimization objective, and execute the reorganized dataflow graph on the reconfigurable processor.
    Type: Application
    Filed: October 29, 2025
    Publication date: February 26, 2026
    Applicant: SambaNova Systems, Inc.
    Inventors: Arnav GOEL, Ravinder KUMAR, Arjun Rajiv SABNIS, Qi ZHENG, Neal SANGHVI
  • Patent number: 12554473
    Abstract: A system is presented that includes a communication link, a runtime processor, and a reconfigurable processor. The reconfigurable processor is adapted for generating an interrupt to the runtime processor in response to a predetermined event and includes first and second dies arranged in a package, having respective first and second arrays of coarse-grained reconfigurable (CGR) units, and respective first and second communication link interfaces coupled to the communication link. The runtime processor is adapted for configuring the first and second communication link interfaces to provide access to the first and second arrays of coarse-grained reconfigurable units from first and second physical function drivers and from at least one virtual function driver, and the reconfigurable processor is adapted for sending the interrupt to the first or to the second physical function driver and for sending the interrupt to a virtual function driver of the at least one virtual function driver.
    Type: Grant
    Filed: March 7, 2023
    Date of Patent: February 17, 2026
    Assignee: SambaNova Systems, Inc.
    Inventors: Manish K. Shah, Paul Jordan, Maran Wilson, Ravinder Kumar
  • Patent number: 12547389
    Abstract: A data processing system is presented that includes a communication link, a runtime processor, and one or more reconfigurable processors. A reconfigurable processor includes first and second dies arranged in a package, having respective K and L arrays of coarse-grained reconfigurable (CGR) units, and respective first and second communication link interfaces coupled to the communication link. The runtime processor is adapted for configuring the first communication link interface to provide access to the K arrays of CGR units through the communication link from a first physical function driver and from up to M virtual function drivers, and for configuring the second communication link interface to provide access to the K arrays of CGR units of the first die and to the L arrays of CGR units of the second die through the communication link from a second physical function driver and from up to N virtual function drivers.
    Type: Grant
    Filed: February 1, 2023
    Date of Patent: February 10, 2026
    Assignee: SambaNova Systems, Inc.
    Inventors: Manish K. Shah, Paul Jordan, Maran Wilson, Ravinder Kumar
  • Publication number: 20260029527
    Abstract: Methods, systems, and devices for wireless communications are described. In some cases, a first network entity may receive multiple signals via multiple channels, where each signal of the multiple signals includes a same payload, and where multiple Doppler shifts are associated with the multiple signals. The UE may determine, based on multiple phase channel responses associated with the multiple signals, two or more clusters of signals from the multiple signals, where each signal of the multiple signals is associated with a respective phase channel response of the multiple phase channel responses based on a respective Doppler shift. Thus, the UE may detect, based on the two or more clusters, one or more communication conditions.
    Type: Application
    Filed: July 25, 2024
    Publication date: January 29, 2026
    Inventors: Ravinder KUMAR, Paolo MINERO, Chao CHEN, Mahmoud Abdelmoneim ELGENEDY, Hyeong Seok JEONG
  • Publication number: 20250377935
    Abstract: A method is provided for controlling a system of reconfigurable data flow resources and a plurality of transfer resources using a runtime processor that is configured with logic. The method includes using the runtime processor to present a unified interface to the reconfigurable data flow resources and the plurality of transfer resources wherein the unified interface enables attachment of one of the configurable units to every other one of the configurable units. The method further includes using the runtime processor to control execution of a plurality of application graphs based on an execution file wherein the application graphs are representations of how the configurable units interact to exchange data to provide data flow with each other through the unified interface, the execution file including topologies for subarrays of configurable units with the topologies indicating how to load the configuration files.
    Type: Application
    Filed: June 18, 2025
    Publication date: December 11, 2025
    Applicant: SambaNova Systems, Inc.
    Inventors: Ravinder KUMAR, Conrad Alexander TURLIK, Arnav GOEL, Qi ZHENG, Raghunath SHENBAGAM, Anand MISRA, Ananda Reddy VAYYALA, Pushkar Shridhar NANDKAR
  • Publication number: 20250374305
    Abstract: Various aspects of the present disclosure generally relate to wireless communication. In some aspects, a user equipment (UE) may receive a first physical broadcast channel (PBCH) communication on a channel. The UE may decode the first PBCH communication as a decoded PBCH payload. The UE may reencode the decoded PBCH payload as a first pilot signal. The UE may receive a first data communication with first data. The UE may correct the channel for the first data based on the first pilot signal. The UE may decode the first data. Numerous other aspects are described.
    Type: Application
    Filed: June 12, 2025
    Publication date: December 4, 2025
    Inventors: Yuhung KAO, Ravinder KUMAR
  • Publication number: 20250365683
    Abstract: Methods, systems, and devices for wireless communications are described. A user equipment (UE) may decode a first signal received over a broadcast channel during a first synchronization signal block (SSB) occasion to identify a first payload, and determine one or more expected changes between the first payload and a second payload of a second signal expected to be received over the broadcast channel during a second SSB occasion. The UE may update the first payload with the one or more expected changes to determine an updated first payload, and encode the updated first payload as an updated first signal. The UE may receive the second signal over the broadcast channel during the second SSB occasion, and apply the second signal and the updated first signal to a tracking procedure for the UE.
    Type: Application
    Filed: August 7, 2025
    Publication date: November 27, 2025
    Inventors: Ravinder KUMAR, Swarupa Gandhi VUDATA, Vishnu Namboodiri KARAKKAD KESAVAN NAMBOODIRI, Mahendran KAMATCHI, Shivaprasad BOORA
  • Patent number: 12461889
    Abstract: A data processing system including an array of reconfigurable units and a compiler configured to generate to execute a dataflow graph of a user application is disclosed. The dataflow graph includes a sequence of temporal partitions, each temporal partition including a sequence of graph control operations. Also disclosed is an intelligent graph orchestration and execution engine (IGOEE) configured to receive an optimization objective from the complier. The optimization objective can be for minimizing execution time of the reconfigurable processor or maximizing computing resource utilization of the reconfigurable processor. The IGOEE can reorganize the sequence of temporal partitions and the sequence of graph control operations within each temporal partition to satisfy the optimization objective; and execute the reorganized dataflow graph on the reconfigurable processor. A corresponding method is also disclosed herein.
    Type: Grant
    Filed: September 8, 2023
    Date of Patent: November 4, 2025
    Assignee: SambaNova Systems, Inc.
    Inventors: Arnav Goel, Ravinder Kumar, Arjun Sabnis, Qi Zheng, Neal Sanghvi
  • Patent number: 12432545
    Abstract: A method of wireless communication performed by a user equipment (UE), the method including: operating in a mode in which a first subscriber identity module (SIM) is designated as a default data subscription (DDS) and a second SIM is designated as a non-default data subscription (nDDS), including the first SIM being active and the second SIM being idle; determining positions of uplink symbols and downlink symbols within a slot format of the first SIM; causing a hardware switch of the UE to couple the second SIM to an antenna of the UE during a first symbol that is configured as uplink or flexible; and performing a page decode operation by the second SIM while the second SIM is coupled to the antenna.
    Type: Grant
    Filed: December 8, 2021
    Date of Patent: September 30, 2025
    Assignee: QUALCOMM Incorporated
    Inventors: Priyangshu Ghosh, Raveesh Juneja, Ravinder Kumar
  • Patent number: 12413530
    Abstract: The disclosed technology relates to link-based resource allocation for a pool of reconfigurable processors. Resource allocation is provided for reconfigurable processors based on link bandwidths and link latencies. Runtime logic receives target link bandwidth and target link latency and rated link bandwidth and rated link latency. In response, the runtime logic allocates configuration files for an application, reconfigurable processors, and links between the processors. The runtime logic executes the allocated configuration files using the allocated processors and the allocated links. In another embodiment, the pool of reconfigurable processors comprise a cluster of processing nodes connected through a network.
    Type: Grant
    Filed: June 11, 2024
    Date of Patent: September 9, 2025
    Assignee: SambaNova Systems, Inc.
    Inventors: Raghunath Shenbagam, Ravinder Kumar
  • Patent number: 12402089
    Abstract: Methods, systems, and devices for wireless communications are described. A user equipment (UE) may decode a first signal received over a broadcast channel during a first synchronization signal block (SSB) occasion to identify a first payload, and determine one or more expected changes between the first payload and a second payload of a second signal expected to be received over the broadcast channel during a second SSB occasion. The UE may update the first payload with the one or more expected changes to determine an updated first payload, and encode the updated first payload as an updated first signal. The UE may receive the second signal over the broadcast channel during the second SSB occasion, and apply the second signal and the updated first signal to a tracking procedure for the UE.
    Type: Grant
    Filed: July 29, 2021
    Date of Patent: August 26, 2025
    Assignee: QUALCOMM Incorporated
    Inventors: Ravinder Kumar, Swarupa Gandhi Vudata, Vishnu Namboodiri Karakkad Kesavan Namboodiri, Mahendran Kamatchi, Shivaprasad Boora
  • Patent number: 12380041
    Abstract: A heterogeneous processing system and method including a host processor with a host memory having allocated buffer space, first and second processors each with memory, multiple data transfer resources, and switch and bus circuitry that communicatively couples the processors and the transfer resources. The first processor executes a first part of an application generating first data stored into the first memory. A data transfer resource is programed to transfer the first data to the buffer space and to transfer the first data from the buffer space into the second memory. The second processor executes a second part of the application generating second data stored into the second memory. The data transfer resources may include a DMA engine in which the buffer space is DMA addressable. One of the first and second processors may be a reconfigurable processor, a compute engine, or a reconfigurable dataflow unit.
    Type: Grant
    Filed: January 19, 2023
    Date of Patent: August 5, 2025
    Assignee: SambaNova Systems, Inc.
    Inventors: Arnav Goel, Neal Sanghvi, Jiayu Bai, Qi Zheng, Ravinder Kumar