Patents by Inventor Ravinder Kumar
Ravinder Kumar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230205585Abstract: A data processing system includes a runtime processor and a pool of reconfigurable data flow resources with memory units, busses, and arrays of physical configurable units. The runtime processor is operatively coupled to the pool of reconfigurable data flow resources and configured to load first and second configuration files for executing first and second user applications on first and second subsets of the arrays of physical configurable units and to assign first and second subsets of the memory units to the first and second user applications. The runtime processor starts execution of the first and second user applications on the first and second subsets of the arrays of physical configurable units, prevents the first user application from accessing the resources allocated to the second user application, and prevents the second user application from accessing resources allocated to the first user application.Type: ApplicationFiled: December 19, 2022Publication date: June 29, 2023Applicant: SambaNova Systems, Inc.Inventors: Ranen CHATTERJEE, Ravinder KUMAR, Raghunath SHENBAGAM, Maran WILSON, Conrad Alexander TURLIK, Arnav GOEL, Arjun SABNIS, Yannan CHEN
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Publication number: 20230179986Abstract: A method of wireless communication performed by a user equipment (UE), the method including: operating in a mode in which a first subscriber identity module (SIM) is designated as a default data subscription (DDS) and a second SIM is designated as a non-default data subscription (nDDS), including the first SIM being active and the second SIM being idle; determining positions of uplink symbols and downlink symbols within a slot format of the first SIM; causing a hardware switch of the UE to couple the second SIM to an antenna of the UE during a first symbol that is configured as uplink or flexible; and performing a page decode operation by the second SIM while the second SIM is coupled to the antenna.Type: ApplicationFiled: December 8, 2021Publication date: June 8, 2023Inventors: Priyangshu GHOSH, Raveesh JUNEJA, Ravinder KUMAR
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Publication number: 20230156536Abstract: Aspects of the present disclosure provide apparatus, methods, processing systems, and computer readable mediums for scheduling and triggering aperiodic channel state information (A-CSI) reporting on a physical uplink control channel (PUCCH) using a downlink grant. An example method generally includes receiving, from a network entity, a downlink grant including a trigger to transmit an aperiodic channel state information (A-CSI) report on a physical uplink control channel (PUCCH), generating the A-CSI report, and transmitting the A-CSI report on the PUCCH using timing and resources indicated in the downlink grant.Type: ApplicationFiled: May 21, 2021Publication date: May 18, 2023Inventors: Ravinder KUMAR, Ahmed ZAKI, Vijayvaradharaj Narayan TIRUCHERAI MURALIDHARAN, Murali MENON, Umesh PHUYAL, Alberto RICO ALVARINO
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Publication number: 20230155369Abstract: An integrated circuit includes an overvoltage protection circuit. The overvoltage protection circuit detects overvoltage events at a pad of the integrated circuit. The overvoltage protection circuit generates a max voltage signal that is the greater of the voltage at the pad and a supply voltage of the integrated circuit. The overvoltage protection circuit disables a PMOS transistor coupled to the pad by supplying the max voltage signal to the gate of the PMOS transistor when an overvoltage event is present at the pad.Type: ApplicationFiled: January 20, 2023Publication date: May 18, 2023Applicants: STMICROELECTRONICS (ROUSSET) SAS, STMicroelectronics International N.V.Inventors: Manoj KUMAR, Ravinder KUMAR, Nicolas DEMANGE
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Patent number: 11625283Abstract: The technology disclosed relates to inter-processor execution of configuration files on reconfigurable processors using smart network interface controller (SmartNIC) buffers. In particular, the technology disclosed relates to a runtime logic that is configured to execute configuration files that define applications and process application data for applications using a first reconfigurable processor and a second reconfigurable processor. The execution includes streaming configuration data in the configuration files and the application data between the first reconfigurable processor and the second reconfigurable processor using one or more SmartNIC buffers.Type: GrantFiled: November 9, 2021Date of Patent: April 11, 2023Assignee: SambaNova Systems, Inc.Inventors: Ram Sivaramakrishnan, Sumti Jairath, Emre Ali Burhan, Manish K. Shah, Raghu Prabhakar, Ravinder Kumar, Arnav Goel, Ranen Chatterjee, Gregory Frederick Grohoski, Kin Hing Leung, Dawei Huang, Manoj Unnikrishnan, Martin Russell Raumann, Bandish B. Shah
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Patent number: 11625284Abstract: The technology disclosed relates to inter-node execution of configuration files on reconfigurable processors using smart network interface controller (SmartNIC) buffers. In particular, the technology disclosed relates to a runtime logic that is configured to execute configuration files that define applications and process application data for applications using a first reconfigurable processor on a first node, and a second host processor on a second node. The execution includes streaming configuration data in the configuration files and the application data between the first reconfigurable processor and the second host processor using one or more SmartNIC buffers.Type: GrantFiled: November 9, 2021Date of Patent: April 11, 2023Assignee: SambaNova Systems, Inc.Inventors: Ram Sivaramakrishnan, Sumti Jairath, Emre Ali Burhan, Manish K. Shah, Raghu Prabhakar, Ravinder Kumar, Arnav Goel, Ranen Chatterjee, Gregory Frederick Grohoski, Kin Hing Leung, Dawei Huang, Manoj Unnikrishnan, Martin Russell Raumann, Bandish B. Shah
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Patent number: 11609798Abstract: The technology disclosed relates to runtime execution of configuration files on reconfigurable processors with varying configuration granularity. In particular, the technology disclosed relates to a runtime logic that is configured to receive a set of configuration files for an application, and load and execute a first subset of configuration files in the set of configuration files and associated application data on a first reconfigurable processor. The first reconfigurable processor has a first level of configurable granularity. The runtime logic is further configured to load and execute a second subset of configuration files in the set of configuration files and associated application data on a second reconfigurable processor. The second reconfigurable processor has a second level of configurable granularity that is different from the first level of configurable granularity.Type: GrantFiled: November 9, 2021Date of Patent: March 21, 2023Assignee: SambaNova Systems, Inc.Inventors: Ram Sivaramakrishnan, Sumti Jairath, Emre Ali Burhan, Manish K. Shah, Raghu Prabhakar, Ravinder Kumar, Arnav Goel, Ranen Chatterjee, Gregory Frederick Grohoski, Kin Hing Leung, Dawei Huang, Manoj Unnikrishnan, Martin Russell Raumann, Bandish B. Shah
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Patent number: 11575254Abstract: An integrated circuit includes an overvoltage protection circuit. The overvoltage protection circuit detects overvoltage events at a pad of the integrated circuit. The overvoltage protection circuit generates a max voltage signal that is the greater of the voltage at the pad and a supply voltage of the integrated circuit. The overvoltage protection circuit disables a PMOS transistor coupled to the pad by supplying the max voltage signal to the gate of the PMOS transistor when an overvoltage event is present at the pad.Type: GrantFiled: November 11, 2020Date of Patent: February 7, 2023Assignees: STMICROELECTRONICS INTERNATIONAL N.V., STMICROELECTRONICS (ROUSSET) SASInventors: Manoj Kumar, Ravinder Kumar, Nicolas Demange
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Publication number: 20230037028Abstract: Methods, systems, and devices for wireless communications are described. A user equipment (UE) may decode a first signal received over a broadcast channel during a first synchronization signal block (SSB) occasion to identify a first payload, and determine one or more expected changes between the first payload and a second payload of a second signal expected to be received over the broadcast channel during a second SSB occasion. The UE may update the first payload with the one or more expected changes to determine an updated first payload, and encode the updated first payload as an updated first signal. The UE may receive the second signal over the broadcast channel during the second SSB occasion, and apply the second signal and the updated first signal to a tracking procedure for the UE.Type: ApplicationFiled: July 29, 2021Publication date: February 2, 2023Inventors: Ravinder Kumar, Swarupa Gandhi Vudata, Vishnu Namboodiri Karakkad Kesavan Namboodiri, Mahendran Kamatchi, Shivaprasad Boora
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Publication number: 20220416792Abstract: An integrated circuit includes an output pad, and I/O driver that drives data to the output pad, and a predriver that controls the I/O driver. The integrated circuit includes maximum voltage generator that receives a first supply voltage and a second supply voltage and outputs to the predriver a maximum voltage corresponding to the higher of the first supply voltage and the second supply voltage.Type: ApplicationFiled: June 17, 2022Publication date: December 29, 2022Applicant: STMicroelectronics International N.V.Inventors: Kailash KUMAR, Ravinder KUMAR
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Publication number: 20220308935Abstract: The technology disclosed relates to interconnect-based resource allocation for reconfigurable processors. In particular, the technology disclosed relates to a runtime logic that is configured to receive target interconnect bandwidth and target interconnect latency, and rated interconnect bandwidth and rated interconnect latency. The runtime logic is further configured to respond by allocating, to configuration files defining an application graph, processing elements in a plurality of processing elements, and interconnects between the processing elements, and executing the configuration files using the allocated processing elements and the allocated interconnects.Type: ApplicationFiled: November 16, 2021Publication date: September 29, 2022Applicant: SambaNova Systems, Inc.Inventors: Raghunath SHENBAGAM, Ravinder KUMAR
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Patent number: 11438115Abstract: Methods, systems, and devices for wireless communications are described to enable a base station to configure additional reference signals, which may be referred to as configured reference signals, to include in a transmission to a user equipment (UE). The UE may transmit a report to the base station, indicating a UE capability for supporting configured reference signals, and the base station may configure a pattern for the configured reference signals. The base station may transmit an indication of the pattern to the UE, where the indication may include one or more characteristics associated with the configured reference signals. The base station may transmit the configured reference signals to the UE according to the pattern, along with one or more baseline reference signals, within an associated transmission. The UE may use the configured reference signals and the baseline reference signals to receive a transmission from the base station.Type: GrantFiled: August 13, 2020Date of Patent: September 6, 2022Assignee: QUALCOMM IncorporatedInventors: Alberto Rico Alvarino, Ahmed Zaki, Ayan Sengupta, Le Liu, Umesh Phuyal, Prasad Reddy Kadiri, Vijayvaradharaj Tirucherai Muralidharan, Ravinder Kumar, Murali Menon
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Publication number: 20220269534Abstract: A method for executing applications in a system comprising general hardware and reconfigurable hardware includes accessing a first execution file comprising metadata storing a first priority indicator associated with a first application, and a second execution file comprising metadata storing a second priority indicator associated with a second application. In an example, use of the reconfigurable hardware is interleaved between the first application and the second application, and the interleaving is scheduled to take into account (i) workload of the reconfigurable hardware and (ii) the first priority indicator and the second priority indicator associated with the first application and the second application, respectively. In an example, when the reconfigurable hardware is used by one of the first and second applications, the general hardware is used by another of the first and second applications.Type: ApplicationFiled: February 25, 2021Publication date: August 25, 2022Applicant: SambaNova Systems, Inc.Inventors: Anand MISRA, Arnav GOEL, Qi ZHENG, Raghunath SHENBAGAM, Ravinder KUMAR
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Patent number: 11391900Abstract: Embodiments of the disclosure relate to an optical fiber cable. The optical fiber cable includes a cable sheath having an interior surface and an exterior surface. The interior surface defines a longitudinal bore and the exterior surface defines an outermost surface of the optical fiber cable. The optical fiber cable also includes a plurality of micromodules disposed within the longitudinal bore. Each micromodule of the plurality of micromodules includes a micromodule jacket surrounding at least one optical fiber. The micromodule jacket of each of the plurality of micromodules is made of a first polymer composition having a first melt temperature, and the cable sheath is made of a second polymer composition having a second melt temperature that is less than the first melt temperature. The first polymer composition and the second polymer compositions are both low smoke, zero halogen materials.Type: GrantFiled: November 6, 2020Date of Patent: July 19, 2022Assignee: CORNING RESEARCH & DEVELOPMENT CORPORATIONInventors: Michael Alexander Heinz, Ravinder Kumar Kinnera
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Patent number: 11392740Abstract: Roughly described, the invention involves a system including a plurality of functional units that execute different segments of a dataflow, and share intermediate results via a peer-to-peer messaging protocol. The functional units are reconfigurable, with different units being reconfigurable at different levels of granularity. The peer-to-peer messaging protocol includes control tokens or other mechanisms by which the consumer of the intermediate results learns that data has been transferred, and in response thereto triggers its next dataflow segment. A host or configuration controller configures the data units with their respective dataflow segments, but once execution of the configured dataflow begins, no host need be involved in orchestrating data synchronization, the transfer of intermediate results, or the triggering of processing after the data are received. Control overhead is therefore minimized.Type: GrantFiled: July 19, 2021Date of Patent: July 19, 2022Assignee: SambaNova Systems, Inc.Inventors: Martin Russell Raumann, Qi Zheng, Bandish B. Shah, Ravinder Kumar, Kin Hing Leung, Sumti Jairath, Gregory Frederick Grohoski
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Publication number: 20220197714Abstract: A system for training parameters of a neural network includes a processing node with a processor reconfigurable at a first level of configuration granularity and a controller reconfigurable at a finer level of configuration granularity. The processor is configured to execute a first dataflow segment of the neural network with training data to generate a predicted output value using a set of neural network parameters, calculate a first intermediate result for a parameter based on the predicted output value, a target output value, and a parameter gradient, and provide the first intermediate result to the controller. The controller is configured to receive a second intermediate result over a network, and execute a second dataflow segment, dependent upon the first intermediate result and the second intermediate result, to generate a third intermediate result indicative of an update of the parameter.Type: ApplicationFiled: January 24, 2022Publication date: June 23, 2022Applicant: SambaNova Systems, Inc.Inventors: Martin Russell RAUMANN, Qi ZHENG, Bandish B. SHAH, Ravinder KUMAR, Kin Hing LEUNG, Sumti JAIRATH, Gregory Frederick GROHOSKI
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Publication number: 20220197711Abstract: The technology disclosed relates to runtime execution of functions across reconfigurable processor. In particular, the technology disclosed relates to a runtime logic that is configured to execute a first set of functions in a plurality of functions and/or data therefor on a first reconfigurable processor, and a second set of functions in the plurality of functions and/or data therefor on additional reconfigurable processors. Functions in the second set of functions and/or the data therefor are transmitted to the additional reconfigurable processors using one or more of a first reconfigurable processor-to-additional reconfigurable processors buffers, and results of executing the functions and/or the data therefor on the additional reconfigurable processors are transmitted to the first reconfigurable processor using one or more of additional reconfigurable processors-to-first reconfigurable processor buffers.Type: ApplicationFiled: November 9, 2021Publication date: June 23, 2022Applicant: SambaNova Systems, Inc.Inventors: Ram Sivaramakrishnan, Sumti Jairath, Emre Ali Burhan, Manish K. Shah, Raghu Prabhakar, Ravinder Kumar, Arnav Goel, Ranen Chatterjee, Gregory Frederick Grohoski, Kin Hing Leung, Dawei Huang, Manoj Unnikrishnan, Martin Russell Raumann, Bandish B. Shah
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Publication number: 20220197713Abstract: The technology disclosed relates to inter-node execution of configuration files on reconfigurable processors using network interface controller (NIC) buffers. In particular, the technology disclosed relates to a runtime logic that is configured to execute configuration files that define applications and application data for applications using a first reconfigurable processor connected to a first host, and a second reconfigurable processor connected to a second host. The first reconfigurable processor is configured to push input data for the applications in a first plurality of buffers. The first host is configured to cause a first network interface controller (NIC) to stream the input data to a second plurality of buffers from the first plurality of buffers. The second host is configured to cause a second NIC to stream the input data to the second reconfigurable processor from the second plurality of buffers.Type: ApplicationFiled: November 9, 2021Publication date: June 23, 2022Applicant: SambaNova Systems, Inc.Inventors: Ram SIVARAMAKRISHNAN, Sumti JAIRATH, Emre Ali BURHAN, Manish K. SHAH, Raghu PRABHAKAR, Ravinder KUMAR, Arnav GOEL, Ranen CHATTERJEE, Gregory Frederick GROHOSKI, Kin Hing LEUNG, Dawei HUANG, Manoj UNNIKRISHNAN, Martin Russell RAUMANN, Bandish B. SHAH
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Publication number: 20220197709Abstract: The technology disclosed relates to runtime execution of configuration files on reconfigurable processors with varying configuration granularity. In particular, the technology disclosed relates to a runtime logic that is configured to receive a set of configuration files for an application, and load and execute a first subset of configuration files in the set of configuration files and associated application data on a first reconfigurable processor. The first reconfigurable processor has a first level of configurable granularity. The runtime logic is further configured to load and execute a second subset of configuration files in the set of configuration files and associated application data on a second reconfigurable processor. The second reconfigurable processor has a second level of configurable granularity that is different from the first level of configurable granularity.Type: ApplicationFiled: November 9, 2021Publication date: June 23, 2022Applicant: SambaNova Systems, Inc.Inventors: Ram SIVARAMAKRISHNAN, Sumti JAIRATH, Emre Ali BURHAN, Manish K. SHAH, Raghu PRABHAKAR, Ravinder KUMAR, Arnav GOEL, Ranen CHATTERJEE, Gregory Frederick GROHOSKI, Kin Hing LEUNG, Dawei HUANG, Manoj UNNIKRISHNAN, Martin Russell RAUMANN, Bandish B. SHAH
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Publication number: 20220197710Abstract: The technology disclosed relates to inter-processor execution of configuration files on reconfigurable processors using smart network interface controller (SmartNIC) buffers. In particular, the technology disclosed relates to a runtime logic that is configured to execute configuration files that define applications and process application data for applications using a first reconfigurable processor and a second reconfigurable processor. The execution includes streaming configuration data in the configuration files and the application data between the first reconfigurable processor and the second reconfigurable processor using one or more SmartNIC buffers.Type: ApplicationFiled: November 9, 2021Publication date: June 23, 2022Applicant: SambaNova Systems, Inc.Inventors: Ram SIVARAMAKRISHNAN, Sumti JAIRATH, Emre Ali BURHAN, Manish K. SHAH, Raghu PRABHAKAR, Ravinder KUMAR, Arnav GOEL, Ranen CHATTERJEE, Gregory Frederick GROHOSKI, Kin Hing LEUNG, Dawei HUANG, Manoj UNNIKRISHNAN, Martin Russell RAUMANN, Bandish B. SHAH