Patents by Inventor Ravindranath Droopad

Ravindranath Droopad has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8847280
    Abstract: An improved insulated gate field effect device is obtained by providing a substrate desirably comprising a III-V semiconductor, having a further semiconductor layer on the substrate adapted to contain the channel of the device between spaced apart source-drain electrodes formed on the semiconductor layer. A dielectric layer is formed on the semiconductor layer. A sealing layer is formed on the dielectric layer and exposed to an oxygen plasma. A gate electrode is formed on the dielectric layer between the source-drain electrodes. The dielectric layer preferably comprises gallium-oxide and/or gadolinium-gallium oxide, and the oxygen plasma is preferably an inductively coupled plasma. A further sealing layer of, for example, silicon nitride is desirably provided above the sealing layer. Surface states and gate dielectric traps that otherwise adversely affect leakage and channel sheet resistance are much reduced.
    Type: Grant
    Filed: November 10, 2011
    Date of Patent: September 30, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Jonathan K. Abrokwah, Ravindranath Droopad, Matthias Passlack
  • Publication number: 20120056246
    Abstract: An improved insulated gate field effect device is obtained by providing a substrate desirably comprising a III-V semiconductor, having a further semiconductor layer on the substrate adapted to contain the channel of the device between spaced apart source-drain electrodes formed on the semiconductor layer. A dielectric layer is formed on the semiconductor layer. A sealing layer is formed on the dielectric layer and exposed to an oxygen plasma. A gate electrode is formed on the dielectric layer between the source-drain electrodes. The dielectric layer preferably comprises gallium-oxide and/or gadolinium-gallium oxide, and the oxygen plasma is preferably an inductively coupled plasma. A further sealing layer of, for example, silicon nitride is desirably provided above the sealing layer. Surface states and gate dielectric traps that otherwise adversely affect leakage and channel sheet resistance are much reduced.
    Type: Application
    Filed: November 10, 2011
    Publication date: March 8, 2012
    Applicant: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Jonathan K. Abrokwah, Ravindranath Droopad, Matthias Passlack
  • Patent number: 8105925
    Abstract: An improved insulated gate field effect device (60) is obtained by providing a substrate (20) desirably comprising a III-V semiconductor, having a further semiconductor layer (22) on the substrate (20) adapted to contain the channel (230) of the device (60) between spaced apart source-drain electrodes (421, 422) formed on the semiconductor layer (22). A dielectric layer (24) is formed on the semiconductor layer (22). A sealing layer (28) is formed on the dielectric layer (24) and exposed to an oxygen plasma (36). A gate electrode (482) is formed on the dielectric layer (24) between the source-drain electrodes (421, 422). The dielectric layer (24) preferably comprises gallium-oxide (25) and/or gadolinium-gallium oxide (26, 27), and the oxygen plasma (36) is preferably an inductively coupled plasma. A further sealing layer (44) of, for example, silicon nitride is desirably provided above the sealing layer (28).
    Type: Grant
    Filed: July 30, 2008
    Date of Patent: January 31, 2012
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Jonathan K. Abrokwah, Ravindranath Droopad, Matthias Passlack
  • Patent number: 7799647
    Abstract: A method of forming a semiconductor structure includes forming a channel layer; forming a superlattice barrier layer overlying the channel layer, and forming a gate dielectric overlying the superlattice barrier layer. The superlattice barrier layer includes alternating first and second layers of barrier material. In addition, the superlattice barrier layer is configured for increasing a transconductance of the semiconductor device by at least a factor of three over a semiconductor device absent such superlattice barrier layer.
    Type: Grant
    Filed: July 31, 2007
    Date of Patent: September 21, 2010
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Ravindranath Droopad, Matthias Passlack, Karthik Rajagopalan
  • Patent number: 7692224
    Abstract: A method of forming a portion (10) of a compound semiconductor MOSFET structure comprises forming a compound semiconductor layer structure (14) and an oxide layer (20) overlying the same. Forming the compound semiconductor structure (14) includes forming at least one channel material (16) and a group-III rich surface termination layer (18) overlying the at least one channel material. Forming the oxide layer (20) includes forming the oxide layer to overlie the group-III rich surface termination layer and comprises one of (a) depositing essentially congruently evaporating oxide of at least one of (a(i)) a ternary oxide and (a(ii)) an oxide more complex than a ternary oxide and (b) depositing oxide molecules, with use of at least one of (b(i)) a ternary oxide and (b(ii)) an oxide more complex than a ternary oxide.
    Type: Grant
    Filed: September 28, 2007
    Date of Patent: April 6, 2010
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Ravindranath Droopad, Matthias Passlack
  • Patent number: 7682912
    Abstract: A method of forming a III-V compound semiconductor structure (10) comprises providing a III-V compound semiconductor substrate including a semi-insulating substrate (12) having at least one epitaxial layer formed thereon and further having a gate insulator (14) overlying the at least one epitaxial layer. The at least one epitaxial layer formed on the semi-insulating substrate comprises an epi-structure suitable for use in the formation of a channel of a III-V compound semiconductor MOSFET device, wherein the channel (30) having a first polarity. The method further comprises forming a charge layer (22) at a surface of the gate insulator, the charge layer having a second polarity, wherein the second polarity is opposite to the first polarity.
    Type: Grant
    Filed: October 31, 2006
    Date of Patent: March 23, 2010
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Matthias Passlack, Ravindranath Droopad, Karthik Rajagopalan
  • Publication number: 20100025729
    Abstract: An improved insulated gate field effect device (60) is obtained by providing a substrate (20) desirably comprising a III-V semiconductor, having a further semiconductor layer (22) on the substrate (20) adapted to contain the channel (230) of the device (60) between spaced apart source-drain electrodes (421, 422) formed on the semiconductor layer (22). A dielectric layer (24) is formed on the semiconductor layer (22). A sealing layer (28) is formed on the dielectric layer (24) and exposed to an oxygen plasma (36). A gate electrode (482) is formed on the dielectric layer (24) between the source-drain electrodes (421, 422). The dielectric layer (24) preferably comprises gallium-oxide (25) and/or gadolinium-gallium oxide (26, 27), and the oxygen plasma (36) is preferably an inductively coupled plasma. A further sealing layer (44) of, for example, silicon nitride is desirably provided above the sealing layer (28).
    Type: Application
    Filed: July 30, 2008
    Publication date: February 4, 2010
    Applicant: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Jonathan K. Abrokwah, Ravindranath Droopad, Matthias Passlack
  • Publication number: 20090085073
    Abstract: A method of forming a portion (10) of a compound semiconductor MOSFET structure comprises forming a compound semiconductor layer structure (14) and an oxide layer (20) overlying the same. Forming the compound semiconductor structure (14) includes forming at least one channel material (16) and a group-III rich surface termination layer (18) overlying the at least one channel material. Forming the oxide layer (20) includes forming the oxide layer to overlie the group-III rich surface termination layer and comprises one of (a) depositing essentially congruently evaporating oxide of at least one of (a(i)) a ternary oxide and (a(ii)) an oxide more complex than a ternary oxide and (b) depositing oxide molecules, with use of at least one of (b(i)) a ternary oxide and (b(ii)) an oxide more complex than a ternary oxide.
    Type: Application
    Filed: September 28, 2007
    Publication date: April 2, 2009
    Inventors: Ravindranath Droopad, Matthias Passlack
  • Publication number: 20090032802
    Abstract: A method of forming a semiconductor structure comprises forming a channel layer; forming a superlattice barrier layer overlying the channel layer, and forming a gate dielectric overlying the superlattice barrier layer. The superlattice barrier layer includes a plurality of alternating first and second layers of barrier material. In addition, the superlattice barrier layer is configured for increasing a transconductance of the semiconductor device by at least a factor of three over a semiconductor device absent such superlattice barrier layer.
    Type: Application
    Filed: July 31, 2007
    Publication date: February 5, 2009
    Inventors: Ravindranath Droopad, Matthias Passlack, Karthik Rajagopalan
  • Patent number: 7442654
    Abstract: A method of forming a dielectric layer structure on a supporting semiconductor structure having a first surface comprises providing a first beam of oxide; depositing a first layer of oxide on the first surface of the supporting semiconductor structure using the first beam of oxide, wherein the first layer of oxide has a second surface; terminating the first beam of oxide, and concurrently providing a second beam of oxide, a beam of metal and a beam of oxygen, wherein the first and second beams of oxide are separate and distinct beams of oxide; and depositing a second layer of oxide on the second surface simultaneously using the second beam of oxide, the beam of metal, and the beam of oxygen.
    Type: Grant
    Filed: September 30, 2005
    Date of Patent: October 28, 2008
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Ravindranath Droopad, Matthias Passlack
  • Publication number: 20080102607
    Abstract: A method of forming a III-V compound semiconductor structure (10) comprises providing a III-V compound semiconductor substrate including a semi-insulating substrate (12) having at least one epitaxial layer formed thereon and further having a gate insulator (14) overlying the at least one epitaxial layer. The at least one epitaxial layer formed on the semi-insulating substrate comprises an epi-structure suitable for use in the formation of a channel of a III-V compound semiconductor MOSFET device, wherein the channel (30) having a first polarity. The method further comprises forming a charge layer (22) at a surface of the gate insulator, the charge layer having a second polarity, wherein the second polarity is opposite to the first polarity.
    Type: Application
    Filed: October 31, 2006
    Publication date: May 1, 2008
    Inventors: Matthias Passlack, Ravindranath Droopad, Karthik Rajagopalan
  • Publication number: 20070148879
    Abstract: A method of forming a metal-insulator-compound semiconductor structure comprises providing an insulator layer overlying a compound semiconductor substrate, the insulator layer having a surface, and forming a metal layer on the surface of the insulator layer using metal organic chemical vapor deposition.
    Type: Application
    Filed: December 22, 2005
    Publication date: June 28, 2007
    Inventors: Matthias Passlack, Ravindranath Droopad
  • Publication number: 20070090405
    Abstract: A method of forming a semiconductor structure comprises providing an insulator layer overlying a III-V compound substrate, the insulator layer having a surface charge layer, the surface charge layer having a deleterious performance effect on the underlying layer or layers of the III-V compound substrate. The method further comprises transforming the surface charge layer into a passivated surface layer, wherein the passivated surface layer reduces the deleterious performance effect on the underlying layer or layers.
    Type: Application
    Filed: September 27, 2005
    Publication date: April 26, 2007
    Inventors: Matthias Passlack, Ravindranath Droopad, Karthik Rajagopalan
  • Publication number: 20070082505
    Abstract: A method of forming an electrically insulating layer (130) on a compound semiconductor (110) comprises: providing a compound semiconductor structure; preparing an upper surface (111) of the compound semiconductor structure to be chemically clean; forming a template (120) on the compound semiconductor structure using a first precursor in a metalorganic chemical vapor deposition (MOCVD) system or a chemical beam epitaxy (CBE) system; and introducing oxygen and a second precursor to the MOCVD system in order to form the electrically insulating layer.
    Type: Application
    Filed: October 11, 2005
    Publication date: April 12, 2007
    Applicant: Freescale Semiconductor, Inc.
    Inventors: Jonathan Abrokwah, Ravindranath Droopad, Matthias Passlack
  • Patent number: 7169619
    Abstract: High quality epitaxial layers of monocrystalline oxide materials (24) can be grown overlying monocrystalline substrates (22) such as large silicon wafers. The monocrystalline oxide layer (24) comprises a layer of monocrystalline oxide spaced apart from the silicon wafer by an amorphous interface layer (28) of silicon oxide. The amorphous interface layer serves as a decoupling layer between the substrate and the buffer layer so that the substrate and the buffer is crystal-graphically, chemically, and dielectrically decoupled. In addition, high quality epitaxial accommodating buffer layers may be formed overlying vicinal substrates using a low pressure, low temperature, alkaline-earth metal-rich process.
    Type: Grant
    Filed: November 19, 2002
    Date of Patent: January 30, 2007
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Yong Liang, Ravindranath Droopad, Xiaoming Hu, Jun Wang, Yi Wei, Zhiyi Yu
  • Patent number: 7105886
    Abstract: A dielectric layer comprised of lanthanum, lutetium, and oxygen that is formed between two conductors or a conductor and a substrate. In one embodiment, the dielectric layer is formed over the substrate without the need for an additional interfacial layer. In another embodiment, the dielectric layer is graded with respect to the lanthanum or lutetium content or in the alternative, may include aluminum. In yet another embodiment, an insulating layer is formed between the conductor or substrate and the dielectric layer or between both the conductor and substrate and the dielectric layer. The dielectric layer is preferably formed by molecular beam epitaxy, but can also be formed by atomic layer chemical vapor deposition, physical vapor deposition, organometallic chemical vapor deposition or pulsed laser deposition.
    Type: Grant
    Filed: July 21, 2004
    Date of Patent: September 12, 2006
    Assignee: Freescale Semiconductor, Inc.
    Inventor: Ravindranath Droopad
  • Patent number: 7105866
    Abstract: High quality epitaxial layers of compound semiconductor materials can be grown overlying large silicon wafers by first growing an accommodating buffer layer on a silicon wafer. The accommodating buffer layer is a layer of monocrystalline oxide spaced apart from the silicon wafer by an amorphous interface layer of silicon oxide. The amorphous interface layer dissipates strain and permits the growth of a high quality monocrystalline oxide accommodating buffer layer. Any lattice mismatch between the accommodating buffer layer and the underlying silicon substrate is taken care of by the amorphous interface layer.
    Type: Grant
    Filed: August 5, 2004
    Date of Patent: September 12, 2006
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Nada El-Zein, Jamal Ramdani, Kurt Eisenbeiser, Ravindranath Droopad
  • Patent number: 7067856
    Abstract: High quality epitaxial layers of compound semiconductor materials can be grown overlying large silicon wafers by first growing an accommodating buffer layer on a silicon wafer. The accommodating buffer layer is a layer of monocrystalline oxide spaced apart from the silicon wafer by an amorphous interface layer of silicon oxide. The amorphous interface layer dissipates strain and permits the growth of a high quality monocrystalline oxide accommodating buffer layer. The accommodating buffer layer is lattice matched to both the underlying silicon wafer and the overlying monocrystalline compound semiconductor layer. Any lattice mismatch between the accommodating buffer layer and the underlying silicon substrate is taken care of by the amorphous interface layer.
    Type: Grant
    Filed: February 2, 2004
    Date of Patent: June 27, 2006
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Jamal Ramdani, Ravindranath Droopad, Lyndee L. Hilt, Kurt Williamson Eisenbeiser
  • Patent number: 7045815
    Abstract: A semiconductor structure exhibiting reduced leakage current is formed of a monocrystalline substrate (101) and a strained-layer heterostructure (105). The strained-layer heterostructure has a first layer (102) formed of a first monocrystalline oxide material having a first lattice constant and a second layer (104) formed of a second monocrystalline oxide material overlying the first layer and having a second lattice constant. The second lattice constant is different from the first lattice constant. The second layer creates strain within the oxide material layers, at the interface between the first and second oxide material layers of the heterostructure, and at the interface of the substrate and the first layer, which changes the energy band offset at the interface of the substrate and the first layer.
    Type: Grant
    Filed: July 30, 2002
    Date of Patent: May 16, 2006
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Zhiyi Yu, Ravindranath Droopad
  • Patent number: 7005717
    Abstract: Circuit (10) has a dual layer gate dielectric (29) formed over a semiconductor substrate (14). The gate dielectric includes an amorphous layer (40) and a monocrystalline layer (42). The monocrystalline layer typically has a higher dielectric constant than the amorphous layer.
    Type: Grant
    Filed: May 14, 2004
    Date of Patent: February 28, 2006
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Kurt Eisenbeiser, Jun Wang, Ravindranath Droopad