Patents by Inventor Ravindranath V. Mahajan

Ravindranath V. Mahajan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11049798
    Abstract: An integrated circuit (IC) package comprising a-substrate having a first side and an opposing a second side, and a bridge die within the substrate. The bridge die comprises a plurality of vias extending from a first side to a second side of the-bridge die. The-bridge die comprises a first plurality of pads on the first side of the bridge die and a second plurality of pads on the second side. The plurality of vias interconnect snes of the first plurality of pads to ones of the second plurality of pads. The bridge die comprises an adhesive film over a layer of silicon oxide on the second side of the bridge die.
    Type: Grant
    Filed: June 28, 2019
    Date of Patent: June 29, 2021
    Assignee: Intel Corporation
    Inventors: Aditya S. Vaidya, Ravindranath V. Mahajan, Digvijay A. Raorane, Paul R. Start
  • Publication number: 20210195798
    Abstract: Embodiments include semiconductor packages. A semiconductor package includes dies on a package substrate, an integrated heat spreader (IHS) with a lid and sidewalls over the dies and package substrate, and a heatsink and a thermal interface material respectively on the IHS. The semiconductor package includes a vapor chamber defined by a surface of the package substrate and surfaces of the lid and sidewalls, and a wick layer in the vapor chamber. The wick layer is on the dies, package substrate, and IHS, where the vapor chamber has a vapor space defined by surfaces of the wick layer and lid of the IHS. The sidewalls are coupled to the package substrate with a sealant that hermetically seals the vapor chamber with the surfaces of the package substrate and the sidewalls and lid. The wick layer has a uniform or non-uniform thickness, and has porous materials including metals, powders, or graphite.
    Type: Application
    Filed: December 20, 2019
    Publication date: June 24, 2021
    Inventors: Nicholas NEAL, Nicholas S. HAEHN, Je-Young CHANG, Kyle ARRINGTON, Aaron MCCANN, Edvin CETEGEN, Ravindranath V. MAHAJAN, Robert L. SANKMAN, Ken P. HACKENBERG, Sergio A. CHAN ARGUEDAS
  • Publication number: 20210125897
    Abstract: Embodiments include a semiconductor package with a thermoelectric cooler (TEC), a method to form such semiconductor package, and a semiconductor packaged system. The semiconductor package includes a die with a plurality of backend layers on a package substrate. The backend layers couple the die to the package substrate. The semiconductor package includes the TEC in the backend layers of the die. The TEC includes a plurality of N-type layers, a plurality of P-type layers, and first and second conductive layers. The first conductive layer is directly coupled to outer regions of bottom surfaces of the N-type and P-type layers, and the second conductive layer is directly coupled to inner regions of top surfaces of the N-type and P-type layers. The first conductive layer has a width greater than a width of the second conductive layer. The N-type and P-type layers are directly disposed between the first and second conductive layers.
    Type: Application
    Filed: October 28, 2019
    Publication date: April 29, 2021
    Inventors: Krishna Vasanth VALAVALA, Ravindranath V. MAHAJAN, Chandra Mohan JHA
  • Patent number: 10978423
    Abstract: A package assembly includes a substrate extending from a first substrate end to a second substrate end. A plurality of conductive traces extend along the substrate. A plurality of contacts are coupled with the respective conductive traces of the plurality of conductive traces. Each of the contacts of the plurality of contacts includes a contact pad coupled with a respective conductive trace of the plurality of conductive traces, and a contact post coupled with the contact pad, the contact post extends from the contact pad. A package cover layer is coupled over the plurality of contact posts. The plurality of contact posts are configured to penetrate the package cover layer and extend to a raised location above the package cover layer.
    Type: Grant
    Filed: December 22, 2015
    Date of Patent: April 13, 2021
    Assignee: Intel Corporation
    Inventors: Dae-Woo Kim, Sujit Sharan, Ravindranath V. Mahajan
  • Publication number: 20210043570
    Abstract: Embodiments include semiconductor packages and methods to form the semiconductor packages. A semiconductor package includes a bridge with a hybrid layer on a high-density packaging (HDP) substrate, a plurality of dies over the bridge and the HDP substrate, and a plurality of through mold vias (TMVs) on the HDP substrate. The bridge is coupled between the dies and the HDP substrate. The bridge is directly coupled to two dies of the dies with the hybrid layer, where a top surface of the hybrid layer of the bridge is directly on bottom surfaces of the dies, and where a bottom surface of the bridge is directly on a top surface of the HDP substrate. The TMVs couple the HDP substrate to the dies, and have a thickness that is substantially equal to a thickness of the bridge. The hybrid layer includes conductive pads, surface finish, and/or dielectric.
    Type: Application
    Filed: August 7, 2019
    Publication date: February 11, 2021
    Inventors: Sanka GANESAN, Kevin MCCARTHY, Leigh M. TRIBOLET, Debendra MALLIK, Ravindranath V. MAHAJAN, Robert L. SANKMAN
  • Publication number: 20210035911
    Abstract: Embodiments include semiconductor packages and methods to form the semiconductor packages. A semiconductor package includes a bridge over a glass patch. The bridge is coupled to the glass patch with an adhesive layer. The semiconductor package also includes a high-density packaging (HDP) substrate over the bridge and the glass patch. The HDP substrate is conductively coupled to the glass patch with a plurality of through mold vias (TMVs). The semiconductor package further includes a plurality of dies over the HDP substrate, and a first encapsulation layer over the TMVs, the bridge, the adhesive layer, and the glass patch. The HDP substrate includes a plurality of conductive interconnects that conductively couple the dies to the bridge and glass patch. The bridge may be an embedded multi-die interconnect bridge (EMIB), where the EMIB is communicatively coupled to the dies, and the glass patch includes a plurality of through glass vias (TGVs).
    Type: Application
    Filed: July 29, 2019
    Publication date: February 4, 2021
    Inventors: Sanka GANESAN, Kevin MCCARTHY, Leigh M. TRIBOLET, Debendra MALLIK, Ravindranath V. MAHAJAN, Robert L. SANKMAN
  • Patent number: 10804117
    Abstract: A method of aligning semiconductor dies having metallic bumps in a mold chase for further processing. A plurality of semiconductor dies are placed in the mold chase at approximately desired locations for further processing. A plurality of magnets in a retainer are associated with the mold chase, the plurality of magnets being associated with respective ones of the plurality of semiconductor dies. The magnetic field of the magnets is applied to align and hold the plurality of dies at the desired location. The plurality of magnets may be adjustably mounted in the retainer so that they can be adjusted to more precisely align the semiconductor dies at the desired locations.
    Type: Grant
    Filed: March 27, 2018
    Date of Patent: October 13, 2020
    Assignee: Intel Corporation
    Inventors: Digvijay Ashokkumar Raorane, Ravindranath V. Mahajan
  • Publication number: 20200312833
    Abstract: The present disclosure is directed to systems and methods of conductively coupling a plurality of relatively physically small core dies to a relatively physically larger base die using an electrical mesh network that is formed in whole or in part in, on, across, or about all or a portion of the base die. Electrical mesh networks beneficially permit the positioning of the cores in close proximity to support circuitry carried by the base die. The minimal separation between the core circuitry and the support circuitry advantageously improves communication bandwidth while reducing power consumption. Each of the cores may include functionally dedicated circuitry such as processor core circuitry, field programmable logic, memory, or graphics processing circuitry. The use of core dies beneficially and advantageously permits the use of a wide variety of cores, each having a common or similar interface to the electrical mesh network.
    Type: Application
    Filed: June 15, 2020
    Publication date: October 1, 2020
    Applicant: INTEL CORPORATION
    Inventors: WILFRED GOMES, MARK T. BOHR, RAJESH KUMAR, ROBERT L. SANKMAN, RAVINDRANATH V. MAHAJAN, WESLEY D. MC CULLOUGH
  • Publication number: 20200258759
    Abstract: Techniques and mechanisms for conducting heat with a packaged integrated circuit (IC) device. In an embodiment, the IC device comprises a package substrate and one or more IC dies coupled thereto, where a thermal conductor of the IC device extends through the package substrate. A thermal conductivity of the thermal conductor is more than 20 Watts per meter per degree Kelvin (W/mK). In another embodiment, thermal conductor further extends at least partially through a mold compound disposed on the one or more IC dies.
    Type: Application
    Filed: September 29, 2017
    Publication date: August 13, 2020
    Inventors: Wilfred GOMES, Ravindranath V. MAHAJAN, Ram S. VISWANATH
  • Publication number: 20200211969
    Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises, a package substrate, an interposer on the package substrate, a first die cube and a second die cube on the interposer, wherein the interposer includes conductive traces for electrically coupling the first die cube to the second die cube, a die on the package substrate, and an embedded multi-die interconnect bridge (EMIB) in the package substrate, wherein the EMIB electrically couples the interposer to the die.
    Type: Application
    Filed: December 28, 2018
    Publication date: July 2, 2020
    Inventors: MD Altaf HOSSAIN, Ankireddy NALAMALPU, Dheeraj SUBBAREDDY, Robert SANKMAN, Ravindranath V. MAHAJAN, Debendra MALLIK, Ram S. VISWANATH, Sandeep B. SANE, Sriram SRINIVASAN, Rajat AGARWAL, Aravind DASU, Scott WEBER, Ravi GUTALA
  • Patent number: 10685947
    Abstract: The present disclosure is directed to systems and methods of conductively coupling a plurality of relatively physically small core dies to a relatively physically larger base die using an electrical mesh network that is formed in whole or in part in, on, across, or about all or a portion of the base die. Electrical mesh networks beneficially permit the positioning of the cores in close proximity to support circuitry carried by the base die. The minimal separation between the core circuitry and the support circuitry advantageously improves communication bandwidth while reducing power consumption. Each of the cores may include functionally dedicated circuitry such as processor core circuitry, field programmable logic, memory, or graphics processing circuitry. The use of core dies beneficially and advantageously permits the use of a wide variety of cores, each having a common or similar interface to the electrical mesh network.
    Type: Grant
    Filed: January 12, 2018
    Date of Patent: June 16, 2020
    Assignee: Intel Corporation
    Inventors: Wilfred Gomes, Mark T. Bohr, Rajesh Kumar, Robert L. Sankman, Ravindranath V. Mahajan, Wesley D. Mc Cullough
  • Publication number: 20200185289
    Abstract: An apparatus is provided which comprises: a plurality of dielectric layers forming a substrate, a plurality of first conductive contacts on a first surface of the substrate, a cavity in the first surface of the substrate defining a second surface parallel to the first surface, a plurality of second conductive contacts on the second surface of the substrate, one or more integrated circuit die(s) coupled with the second conductive contacts, and mold material at least partially covering the one or more integrated circuit die(s) and the first conductive contacts. Other embodiments are also disclosed and claimed.
    Type: Application
    Filed: December 27, 2016
    Publication date: June 11, 2020
    Applicant: Intel Corporation
    Inventors: Mitul MODI, Robert L. SANKMAN, Debendra MALLIK, Ravindranath V. MAHAJAN, Amruthavalli P. ALUR, Yikang DENG, Eric J. LI
  • Publication number: 20200144186
    Abstract: A package substrate and a package assembly including a package substrate including a substrate body including a plurality of first contact points on a surface thereof configured for electrical connection to a first die and a plurality of second contact points on the surface configured for electrical connection to a second die; and a bridge coupled to the substrate body, the bridge including active device circuitry that is coupled to ones of the plurality of first contact points and ones of the plurality of second contact points. A method of forming a package assembly including coupling a first die to a package substrate, the package substrate including a bridge substrate including active device circuitry; and coupling a second die to the package substrate, wherein coupling the first die and the second die to the package substrate includes coupling the first die and the second die to the active circuitry.
    Type: Application
    Filed: September 13, 2017
    Publication date: May 7, 2020
    Inventors: Thomas P. THOMAS, Wilfred GOMES, Ravindranath V. MAHAJAN, Rajesh KUMAR, Mark T. BOHR, Dheeraj SUBBAREDDY, Ankireddy NALAMALPU, Mahesh KUMASHIKAR
  • Publication number: 20200066640
    Abstract: Embodiments are generally directed to hybrid technology 3-D die stacking. An embodiment of an apparatus includes a TSV array substrate including through silicon vias (TSVs) and wire bond contacts; a stack of one or more wire bond dies; and a package coupled with the TSV substrate by a first interconnect, wherein the one or more wire bond dies are connected via one or more wires to one or more wire bond contacts of the TSV array substrate, and wherein the TSV array substrate provides connections to the for each of the one or more wire bond dies.
    Type: Application
    Filed: December 26, 2015
    Publication date: February 27, 2020
    Inventors: Arnab SARKAR, Ravindranath V. MAHAJAN
  • Publication number: 20190363049
    Abstract: A multiple die package is described that has an embedded bridge to connect the dies. One example is a microelectronic package that includes a package substrate, a silicon bridge embedded in the substrate, a first interconnect having a first plurality of contacts at a first location of the silicon bridge, a second interconnect having a second plurality of contacts at a second location of the silicon bridge, a third interconnect having a third plurality of contacts at a third location of the silicon bridge, and an electrically conductive line in the silicon bridge connecting a contact of the first interconnect, a contact of the second interconnect, and a contact of the third interconnect each to each other.
    Type: Application
    Filed: March 22, 2017
    Publication date: November 28, 2019
    Inventors: Yidnekachew S. MEKONNEN, Kemel AYGUN, Ravindranath V. MAHAJAN, Christopher S. BALDWIN, Rajasekaran SWAMINATHAN
  • Patent number: 10468331
    Abstract: A heat management system may include a die package. The die package may include a housing. The housing may include a housing surface. The housing may include a housing inlet port. The housing inlet port may be in communication with the housing surface. The housing may include a housing outlet port. The housing outlet port may be in communication with the housing surface. The heat management system may include a manifold. The manifold may be configured to couple with the housing. The manifold may include a manifold surface. The manifold surface may be configured to mate with the housing surface. The manifold may include a manifold inlet port. The manifold inlet port may be in communication with the manifold surface. The manifold may include a manifold outlet port. The manifold outlet port may be in communication with the manifold surface.
    Type: Grant
    Filed: January 12, 2018
    Date of Patent: November 5, 2019
    Assignee: Intel Corporation
    Inventors: Je-young Chang, Jae W. Kim, Ravindranath V. Mahajan, Blake Rogers, Devdatta Kulkarni
  • Publication number: 20190326198
    Abstract: An integrated circuit (IC) package comprising a-substrate having a first side and an opposing a second side, and a bridge die within the substrate. The bridge die comprises a plurality of vias extending from a first side to a second side of the-bridge die. The-bridge die comprises a first plurality of pads on the first side of the bridge die and a second plurality of pads on the second side. The plurality of vias interconnect snes of the first plurality of pads to ones of the second plurality of pads. The bridge die comprises an adhesive film over a layer of silicon oxide on the second side of the bridge die.
    Type: Application
    Filed: June 28, 2019
    Publication date: October 24, 2019
    Applicant: Intel Corporation
    Inventors: Aditya S. Vaidya, Ravindranath V. Mahajan, Digvijay A. Raorane, Paul R. Start
  • Publication number: 20190318993
    Abstract: A device and method of utilizing a repeater circuit to extend the viable length of an interconnect bridge. Integrated circuit packages using a repeater circuit in a repeater die, embedded in a substrate, and included in an interconnect bridge are show. Methods of connecting semiconductor dies using interconnect bridges coupled with repeater circuits are shown.
    Type: Application
    Filed: December 28, 2016
    Publication date: October 17, 2019
    Inventors: Ravindranath V. Mahajan, Zhiguo Qian, Henning Braunisch, Kemal Aygun, Sujit Sharan
  • Publication number: 20190304809
    Abstract: A method of aligning semiconductor dies having metallic bumps in a mold chase for further processing. A plurality of semiconductor dies are placed in the mold chase at approximately desired locations for further processing. A plurality of magnets in a retainer are associated with the mold chase, the plurality of magnets being associated with respective ones of the plurality of semiconductor dies. The magnetic field of the magnets is applied to align and hold the plurality of dies at the desired location. The plurality of magnets may be adjustably mounted in the retainer so that they can be adjusted to more precisely align the semiconductor dies at the desired locations.
    Type: Application
    Filed: March 27, 2018
    Publication date: October 3, 2019
    Inventors: Digvijay Ashokkumar Raorane, Ravindranath V. Mahajan
  • Publication number: 20190287956
    Abstract: An apparatus is provided comprising: a substrate; a die having a first side and a second side, wherein the die is mounted on the substrate such that the first side of the die faces the substrate, and wherein at least a portion of the first side of the die is removed to form a recess in the die; and a component, wherein at least a part of the component is disposed within the recess in the first die.
    Type: Application
    Filed: December 30, 2016
    Publication date: September 19, 2019
    Applicant: Intel Corporation
    Inventors: Digvijay A. Raorane, Ravindranath V. Mahajan