Patents by Inventor Ravindranath V. Mahajan
Ravindranath V. Mahajan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9691711Abstract: An electromagnetic interference shield is described for semiconductor chip packages. In some embodiments, a mold compound is formed over a semiconductor die, the die being over a front side redistribution layer on a side opposite the mold compound, the redistribution layer extending past the die and the mold compound extending around the die to contact the redistribution layer. A plurality of vias are formed in the mold compound vertically toward the redistribution layer, the vias being outside of the die, wherein the bottoms of the vias are over a ground layer of the front side redistribution layer. A continuous conductive shielding film is applied over the mold compound and into the vias, wherein the shielding film in some of the vias directly connects to the ground layer and wherein the shielding film in some of the vias does not directly connect to the ground layer, the redistribution layer connecting the metal film to an external ground so that the vias form a shield.Type: GrantFiled: February 26, 2016Date of Patent: June 27, 2017Assignee: Intel CorporationInventors: Ravindranath V. Mahajan, John S. Guzek, Adel A. Elsherbini, Nitin Ashok Deshpande
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Patent number: 9685421Abstract: The subject matter of the present description relates to methods for the precise integration of microelectronic dice within a multichip package which substantially reduce or eliminate any misalign caused by the movement of the microelectronic dice during the integration process. These methods may include the use of a temporary adhesive in conjunction with a carrier having at least one recess for microelectronic die alignment, the use of a precision molded carrier for microelectronic die alignment, the use of magnetic alignment of microelectronic dice on a reusable carrier, and/or the use of a temporary adhesive with molding processes on a reusable carrier.Type: GrantFiled: June 1, 2015Date of Patent: June 20, 2017Assignee: Intel CorporationInventors: Aleksandar Aleksov, Ravindranath V Mahajan, Omkar Karhade, Nitin Deshpande
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Patent number: 9679843Abstract: Embodiments of a system and methods for localized high density substrate routing are generally described herein. In one or more embodiments an apparatus includes a medium, first and second circuitry elements, an interconnect element, and a dielectric layer. The medium can include low density routing therein. The interconnect element can be embedded in the medium, and can include a plurality of electrically conductive members therein, the electrically conductive member can be electrically coupled to the first circuitry element and the second circuitry element. The interconnect element can include high density routing therein. The dielectric layer can be over the interconnect die, the dielectric layer including the first and second circuitry elements passing therethrough.Type: GrantFiled: February 22, 2016Date of Patent: June 13, 2017Assignee: Intel CorporationInventors: Robert Starkston, Debendra Mallik, John S. Guzek, Chia-Pin Chiu, Deepak Kulkarni, Ravindranath V. Mahajan
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Patent number: 9548410Abstract: An apparatus for collecting solar energy, including a first panel, wherein the first panel allows at least 50% of incident light having a wavelength in the range of 1 nm to 1,500 nm to pass through said panel and a second panel, wherein the second panel allows at least 50% of incident light having a wavelength in the range of 410 nm to 650 nm to pass through said panel. A photovoltaic cell is disposed between the first panel and second panel, which includes a first electrode disposed adjacent to the first panel, a second electrode disposed adjacent to the second panel, a photovoltaic component contacting the first and second electrodes. The photovoltaic component absorbs at least 50% of light having a wavelength in one of the following ranges: greater than 650 nm, less than 410 nm and combinations thereof.Type: GrantFiled: December 17, 2012Date of Patent: January 17, 2017Assignee: INTEL CORPORATIONInventors: Aleksandar Aleksov, Brian S. Doyle, Ravindranath V. Mahajan
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Publication number: 20160379951Abstract: The present disclosure relates to the field of fabricating microelectronic packages, wherein magnetic particles distributed within a solder paste may be used to form a magnetic intermetallic compound interconnect. The intermetallic compound interconnect may be exposed to a magnetic field, which can heat a solder material to a reflow temperature for attachment of microelectronic components comprising the microelectronic packages.Type: ApplicationFiled: December 10, 2014Publication date: December 29, 2016Applicant: Intel CorporationInventors: RAJASEKARAN SWAMINATHAN, RAVINDRANATH V. MAHAJAN
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Patent number: 9526285Abstract: A flexible computing fabric and a method of forming thereof. The flexible computing fabric includes an electronic substrate including one or more channels and including at least two ends. At least one computational element is mounted on the electronic substrate between the two ends and at least one functional element is mounted on the electronic substrate between the two ends. The channels form an interconnect between the elements. In addition, the electronic substrate is flexible and exhibits a flexural modulus in the range of 0.1 GPa to 30 GPa.Type: GrantFiled: December 18, 2012Date of Patent: December 27, 2016Assignee: INTEL CORPORATIONInventors: Aleksandar Aleksov, Ravindranath V. Mahajan, Sairam Agraharam, Ian A. Young, John C. Johnson, Debendra Mallik, John S. Guzek
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Publication number: 20160197037Abstract: Embodiments of a system and methods for localized high density substrate routing are generally described herein. In one or more embodiments an apparatus includes a medium, first and second circuitry elements, an interconnect element, and a dielectric layer. The medium can include low density routing therein. The interconnect element can be embedded in the medium, and can include a plurality of electrically conductive members therein, the electrically conductive member can be electrically coupled to the first circuitry element and the second circuitry element. The interconnect element can include high density routing therein. The dielectric layer can be over the interconnect die, the dielectric layer including the first and second circuitry elements passing therethrough.Type: ApplicationFiled: February 22, 2016Publication date: July 7, 2016Inventors: Robert Starkston, Debendra Mallik, John S. Guzek, Chia-Pin Chiu, Deepak Kulkarni, Ravindranath V. Mahajan
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Publication number: 20160181207Abstract: An electromagnetic interference shield is described for semiconductor chip packages. In some embodiments, a mold compound is formed over a semiconductor die, the die being over a front side redistribution layer on a side opposite the mold compound, the redistribution layer extending past the die and the mold compound extending around the die to contact the redistribution layer. A plurality of vias are formed in the mold compound vertically toward the redistribution layer, the vias being outside of the die, wherein the bottoms of the vias are over a ground layer of the front side redistribution layer. A continuous conductive shielding film is applied over the mold compound and into the vias, wherein the shielding film in some of the vias directly connects to the ground layer and wherein the shielding film in some of the vias does not directly connect to the ground layer, the redistribution layer connecting the metal film to an external ground so that the vias form a shield.Type: ApplicationFiled: February 26, 2016Publication date: June 23, 2016Applicant: Intel CorporationInventors: Ravindranath V. Mahajan, John S. Guzek, Adel A. Elsherbini, Nitin Ashok Deshpande
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Publication number: 20160172320Abstract: The present disclosure relates to the field of fabricating microelectronic packages, wherein magnetic particles distributed within a solder paste may be used to form a magnetic intermetallic compound interconnect. The intermetallic compound interconnect may be exposed to a magnetic field, which can heat a solder material to a reflow temperature for attachment of microelectronic components comprising the microelectronic packages.Type: ApplicationFiled: December 10, 2014Publication date: June 16, 2016Applicant: Intel CorporationInventors: RAJASEKARAN SWAMINATHAN, RAVINDRANATH V. MAHAJAN
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Patent number: 9368455Abstract: An electromagnetic interference shield is described for semiconductor chip packages. In some embodiments, a package has a semiconductor die. a redistribution layer, a mold compound over the die, a plurality of vias through the mold compound and outside the die to form a shield, and a metal film over the vias. and over the mold compound.Type: GrantFiled: March 28, 2014Date of Patent: June 14, 2016Assignee: Intel CorporationInventors: Ravindranath V. Mahajan, John S. Guzek, Adel A. Elsherbini, Nitin Ashok Deshpande
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Publication number: 20160155705Abstract: Embodiments of the present disclosure are directed towards an integrated circuit (IC) package having first and second dies with first and second input/output (I/O) interconnect structures, respectively. The IC package may include a bridge having first and second electrical routing features coupled to a portion of the first and second I/O interconnect structures, respectively. In embodiments, the first and second electrical routing features may be disposed on one side of the bridge; and third electrical routing features may be disposed on an opposite side. The first and second electrical routing features may be configured to route electrical signals between the first die and the second die and the third electrical routing features may be configured to route electrical signals between the one side and the opposite side. The first die, the second die, and the bridge may be embedded in electrically insulating material. Other embodiments may be described and/or claimed.Type: ApplicationFiled: January 22, 2016Publication date: June 2, 2016Inventors: Ravindranath V. Mahajan, Christopher J. Nelson, Omkar G. Karhade, Feras Eid, Nitin A. Deshpande, Shawna M. Liff
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Patent number: 9323327Abstract: A system and method for providing tactile feedback in a user interface. The system includes a tactile feedback assembly configured to communicate with a user interface of an electronic device. The tactile feedback assembly is configured to provide mechanical and/or nerve stimulation to a user during user interaction (e.g. navigation, input of data, etc.) of the user interface. The mechanical and/or nerve stimulation is configured to provide a user with tactile sensation (in the form of the sense of touch) in response to user interaction with the user interface, including, but not limited to, sense of texture and sense of pressure.Type: GrantFiled: December 22, 2012Date of Patent: April 26, 2016Assignee: Intel CorporationInventors: Aleksandar Aleksov, Ravindranath V. Mahajan, Brian S. Doyle
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Patent number: 9275955Abstract: Embodiments of the present disclosure are directed towards an integrated circuit (IC) package having first and second dies with first and second input/output (I/O) interconnect structures, respectively. The IC package may include a bridge having first and second electrical routing features coupled to a portion of the first and second I/O interconnect structures, respectively. In embodiments, the first and second electrical routing features may be disposed on one side of the bridge; and third electrical routing features may be disposed on an opposite side. The first and second electrical routing features may be configured to route electrical signals between the first die and the second die and the third electrical routing features may be configured to route electrical signals between the one side and the opposite side. The first die, the second die, and the bridge may be embedded in electrically insulating material. Other embodiments may be described and/or claimed.Type: GrantFiled: December 18, 2013Date of Patent: March 1, 2016Assignee: INTEL CORPORATIONInventors: Ravindranath V. Mahajan, Christopher J. Nelson, Omkar G. Karhade, Feras Eid, Nitin A. Deshpande, Shawna M. Liff
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Publication number: 20150279789Abstract: An electromagnetic interference shield is described for semiconductor chip packages. In some embodiments, a package has a semiconductor die. a redistribution layer, a mold compound over the die, a plurality of vias through the mold compound and outside the die to form a shield, and a metal film over the vias. and over the mold compound.Type: ApplicationFiled: March 28, 2014Publication date: October 1, 2015Inventors: Ravindranath V. Mahajan, John S. Guzek, Adel A. Elshebini, Nitin Ashok Deshpande
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Publication number: 20150262968Abstract: The subject matter of the present description relates to methods for the precise integration of microelectronic dice within a multichip package which substantially reduce or eliminate any misalign caused by the movement of the microelectronic dice during the integration process. These methods may include the use of a temporary adhesive in conjunction with a carrier having at least one recess for microelectronic die alignment, the use of a precision molded carrier for microelectronic die alignment, the use of magnetic alignment of microelectronic dice on a reusable carrier, and/or the use of a temporary adhesive with molding processes on a reusable carrier.Type: ApplicationFiled: June 1, 2015Publication date: September 17, 2015Applicant: Intel CorporationInventors: Aleksandar Aleksov, Ravindranath V Mahajan, Omkar Karhade, Nitin Deshpande
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Publication number: 20150255411Abstract: Embodiments of the present disclosure are directed towards die-to-die bonding and associated integrated circuit (IC) package configurations. In one embodiment, a package assembly includes a package substrate having a solder resist layer disposed on a first side and a second side disposed opposite to the first side, a first die mounted on the first side and having an active side that is electrically coupled with the package substrate by one or more first die-level interconnects and a second die bonded with the active side of the first die using one or more second die-level interconnects, wherein at least a portion of the second die is disposed in a cavity that extends into the solder resist layer. Other embodiments may be described and/or claimed.Type: ApplicationFiled: March 5, 2014Publication date: September 10, 2015Inventors: Omkar G. Karhade, Debendra Mallik, Ravindranath V. Mahajan, Amruthavalli P. Alur
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Patent number: 9118188Abstract: A wireless charging system includes a microelectronic package (110) containing a system on chip (120) (an SoC), an energy transfer unit (140), and a software protocol (127). The SoC includes a processing device (121), a memory device (122) coupled to the processing device, and a communications device (123) coupled to the processing device and the memory device. The communications device is capable of communicating wirelessly with an external electronic device (130). The energy transfer unit is capable of transferring energy to the external electronic device. The software protocol is implemented in the memory device and is capable of detecting a charging profile of the external electronic device and capable of adjusting a parameter of the energy transfer unit according to a requirement of the charging profile.Type: GrantFiled: December 17, 2012Date of Patent: August 25, 2015Assignee: Intel CorporationInventors: Brian S. Doyle, Aleksandar Aleksov, Ravindranath V. Mahajan
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Patent number: 9076882Abstract: The subject matter of the present description relates to methods for the precise integration of microelectronic dice within a multichip package which substantially reduce or eliminate any misalign caused by the movement of the microelectronic dice during the integration process. These methods may include the use of a temporary adhesive in conjunction with a carrier having at least one recess for microelectronic die alignment, the use of a precision molded carrier for microelectronic die alignment, the use of magnetic alignment of microelectronic dice on a reusable carrier, and/or the use of a temporary adhesive with molding processes on a reusable carrier.Type: GrantFiled: June 3, 2013Date of Patent: July 7, 2015Assignee: Intel CorporationInventors: Aleksandar Aleksov, Ravindranath V Mahajan, Omkar Karhade, Nitin Deshpande
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Publication number: 20150171015Abstract: Embodiments of the present disclosure are directed towards an integrated circuit (IC) package having first and second dies with first and second input/output (I/O) interconnect structures, respectively. The IC package may include a bridge having first and second electrical routing features coupled to a portion of the first and second I/O interconnect structures, respectively. In embodiments, the first and second electrical routing features may be disposed on one side of the bridge; and third electrical routing features may be disposed on an opposite side. The first and second electrical routing features may be configured to route electrical signals between the first die and the second die and the third electrical routing features may be configured to route electrical signals between the one side and the opposite side. The first die, the second die, and the bridge may be embedded in electrically insulating material. Other embodiments may be described and/or claimed.Type: ApplicationFiled: December 18, 2013Publication date: June 18, 2015Inventors: Ravindranath V. Mahajan, Christopher J. Nelson, Omkar G. Karhade, Feras Eid, Nitin A. Deshpande, Shawna M. Liff
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Patent number: 8939347Abstract: The present disclosure relates to the field of fabricating microelectronic packages, wherein magnetic particles distributed within a solder paste may be used to form a magnetic intermetallic compound interconnect. The intermetallic compound interconnect may be exposed to a magnetic field, which can heat a solder material to a reflow temperature for attachment of microelectronic components comprising the microelectronic packages.Type: GrantFiled: April 28, 2010Date of Patent: January 27, 2015Assignee: Intel CorporationInventors: Rajasekaran Swaminathan, Ravindranath V. Mahajan