Abstract: Apparatus and computing systems associated with cache sharing based thread control are described. One embodiment includes a memory to store a thread control instruction and a processor to execute the thread control instruction. The processor is coupled to the memory. The processor includes a first unit to dynamically determine a cache sharing behavior between threads in a multi-threaded computing system and a second unit to dynamically control the composition of a set of threads in the multi-threaded computing system. The composition of the set of threads is based, at least in part, on thread affinity as exhibited by cache-sharing behavior. The thread control instruction controls the operation of the first unit and the second unit.

Abstract: Embodiments of apparatuses, methods, and systems for sharing information between guests in a virtual machine environment are disclosed. In one embodiment, an apparatus includes virtual machine control logic, an execution unit, and a memory management unit. The virtual machine control logic is to transfer control of the apparatus among a host and its guests. The execution unit is to execute an instruction to copy information from a virtual memory address in one guest's virtual address space to a virtual memory address in another guest's virtual address space. The memory management unit is to translate the virtual memory addresses to physical memory addresses.

Abstract: In one embodiment, the present invention includes a method for incrementing a counter value associated with a cache line if the cache line is inserted into a first level cache, and storing the cache line into a second level cache coupled to the first level cache or a third level cache coupled to the second level cache based on the counter value, after eviction from the first level cache. Other embodiments are described and claimed.

Abstract: In one embodiment, the present invention includes a method for maintaining data in a first level cache non-inclusively with data in a second level cache coupled to the first level cache. At the same time, at least a portion of directory information associated with the data in the first level cache may be maintained inclusively with a directory portion of the second level cache. Other embodiments are described and claimed.

Abstract: In one embodiment, the present invention includes a method for associating a first priority indicator with first data stored in a first entry of a cache memory to indicate a priority level of the first data, and updating a count value associated with the first priority indicator. The count value may then be used in determining an appropriate cache line for eviction. Other embodiments are described and claimed.

Abstract: Methods and apparatus to pin a lock in a shared cache are described. In one embodiment, a memory access request is used to pin a lock of one or more cache lines in a shared cache that correspond to the memory access request.

Abstract: In some embodiments, a low overhead mechanism for offloading copy operations is presented. In this regard, a copy agent is introduced to receive a copy request, to notify of copy completion before the copy has been performed, and to perform the copy. Other embodiments are also disclosed and claimed.

Abstract: In one embodiment, the present invention includes a method of analyzing an extensible markup language (XML) file, generating structural information for the XML file, and incorporating the structural information into the XML file. The structural information may correspond to a hierarchy of the file and may further include size information corresponding to elements of the file. In such manner, the structural information may be transmitted with the XML file and used to aid a receiver of the file in parsing. Other embodiments are described and claimed.

Abstract: In general, the disclosure describes a variety of techniques that can enhance packet processing operations.

Abstract: In some embodiments, a method, apparatus and system for an application-aware cache push agent. In this regard, a cache push agent is introduced to push contents of memory into a cache of a processor in response to a memory read by the processor of associated contents. Other embodiments are described and claimed.

Abstract: Methods and apparatus to process cache allocation requests are disclosed. In an example method, a priority level is assigned to a cache allocation request. Based on the priority level, an allocation probability associated with the cache allocation request is identified. Based on the allocation probability, the cache allocation request is identified with either an allocate condition and a bypass condition.