Patents by Inventor Ravishankar Iyer

Ravishankar Iyer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Methods And Apparatuses For Controlling Thread Contention
    Publication number: 20130132969
    Abstract: An apparatus comprises a plurality of cores and a controller coupled to the cores. The controller is to lower an operating point of a first core if a first number based on processor clock cycles per instruction (CPI) associated with a second core is higher than a first threshold. The controller is operable to increase the operating point of the first core if the first number is lower than a second threshold.
    Type: Application
    Filed: December 20, 2012
    Publication date: May 23, 2013
    Inventors: Andrew Herdrich, Ramesh Illikkal, Donald Newell, Ravishankar Iyer, Vineet Chadha
  • Searching a shared cache by using search hints and masked ways
    Patent number: 8412885
    Abstract: In an embodiment of the present invention a method includes: sending request for data to a memory controller; arranging the request for data by order of importance or priority; identifying a source of the request for data; and if the source is an input/output device, masking off P ways in a cache; and allocating ways in filling the cache. Other embodiments are described and claimed.
    Type: Grant
    Filed: November 12, 2009
    Date of Patent: April 2, 2013
    Assignee: Intel Corporation
    Inventors: Liqun Cheng, Zhen Fang, Jeffrey Wilder, Sadagopan Srinivasan, Ravishankar Iyer, Donald Newell
  • Monitoring cache usage in a distributed shared cache
    Patent number: 8392657
    Abstract: An apparatus, method, and system are disclosed. In one embodiment the apparatus includes a cache memory, which a number of sets. Each of the sets in the cache memory have several cache lines. The apparatus also includes at least one process resource table. The process resource table maintains a cache line occupancy count of a number of cache lines. Specifically, the cache line occupancy count for each cache line describes the number of cache lines in the cache storing information utilized by a process running on a computer system. Additionally, the process resource table stores the occupancy count of less cache lines than the total number of cache lines in the cache memory.
    Type: Grant
    Filed: October 9, 2009
    Date of Patent: March 5, 2013
    Assignee: Intel Corporation
    Inventors: Li Zhao, Ravishankar Iyer, Rameshkumar G. Illikkal, Erik G. Hallnor, Martin G. Dixon, Donald K. Newell
  • Delegating a poll operation to another device
    Patent number: 8364862
    Abstract: In one embodiment, the present invention includes a method for handling a registration message received from a host processor, where the registration message delegates a poll operation with respect to a device from the host processor to another component. Information from the message may be stored in a poll table, and the component may send a read request to poll the device and report a result of the poll to the host processor based on a state of the device. Other embodiments are described and claimed.
    Type: Grant
    Filed: June 11, 2009
    Date of Patent: January 29, 2013
    Assignee: Intel Corporation
    Inventors: Michael J. Espig, Zhen Fang, Ravishankar Iyer, David J. Harriman
  • CONTROL OF ON-DIE SYSTEM FABRIC BLOCKS
    Publication number: 20120284486
    Abstract: Methods and apparatus for control of On-Die System Fabric (OSF) blocks are described. In one embodiment, a shadow address corresponding to a physical address may be stored in response to a user-level request and a logic circuitry (e.g., present in an OSF) may determine the physical address from the shadow address. Other embodiments are also disclosed.
    Type: Application
    Filed: July 17, 2012
    Publication date: November 8, 2012
    Inventors: Zhen Fang, Mahesh Wagh, Jasmin Ajanovic, Michael E. Espig, Ravishankar Iyer
  • Scheduling Workloads Based On Cache Asymmetry
    Publication number: 20120233393
    Abstract: In one embodiment, a processor includes a first cache and a second cache, a first core associated with the first cache and a second core associated with the second cache. The caches are of asymmetric sizes, and a scheduler can intelligently schedule threads to the cores based at least in part on awareness of this asymmetry and resulting cache performance information obtained during a training phase of at least one of the threads.
    Type: Application
    Filed: March 8, 2011
    Publication date: September 13, 2012
    Inventors: Xiaowei Jiang, Li Zhao, Ravishankar Iyer
  • Methods And Apparatuses For Controlling Thread Contention
    Publication number: 20120221874
    Abstract: An apparatus comprises a plurality of cores and a controller coupled to the cores. The controller is to lower an operating point of a first core if a first number based on processor clock cycles per instruction (CPI) associated with a second core is higher than a first threshold. The controller is operable to increase the operating point of the first core if the first number is lower than a second threshold.
    Type: Application
    Filed: May 2, 2012
    Publication date: August 30, 2012
    Inventors: Andrew Herdrich, Ramesh Illikkal, Donald Newell, Ravishankar Iyer, Vineet Chadha
  • CIRCUITRY TO SELECT, AT LEAST IN PART, AT LEAST ONE MEMORY
    Publication number: 20120191896
    Abstract: An embodiment may include circuitry to select, at least in part, from a plurality of memories, at least one memory to store data. The memories may be associated with respective processor cores. The circuitry may select, at least in part, the at least one memory based at least in part upon whether the data is included in at least one page that spans multiple memory lines that is to be processed by at least one of the processor cores. If the data is included in the at least one page, the circuitry may select, at least in part, the at least one memory, such that the at least one memory is proximate to the at least one of the processor cores. Many alternatives, variations, and modifications are possible.
    Type: Application
    Filed: January 25, 2011
    Publication date: July 26, 2012
    Inventors: Zhen Fang, Li Zhao, Ravishankar Iyer, Srihari Makineni, Guangdeng Liao
  • Control of on-die system fabric blocks
    Patent number: 8225069
    Abstract: Methods and apparatus for control of On-Die System Fabric (OSF) blocks are described. In one embodiment, a shadow address corresponding to a physical address may be stored in response to a user-level request and a logic circuitry (e.g., present in an OSF) may determine the physical address from the shadow address. Other embodiments are also disclosed.
    Type: Grant
    Filed: March 31, 2009
    Date of Patent: July 17, 2012
    Assignee: Intel Corporation
    Inventors: Zhen Fang, Mahesh Wagh, Jasmin Ajanovic, Michael E Espig, Ravishankar Iyer
  • METHOD, APPARATUS, AND SYSTEM FOR ENERGY EFFICIENCY AND ENERGY CONSERVATION INCLUDING DYNAMIC C0-STATE CACHE RESIZING
    Publication number: 20120173907
    Abstract: Embodiments of systems, apparatuses, and methods for energy-efficient operation of a device are described. In some embodiments, a cache performance indicator of a cache is monitored, and a set of one or more cache performance parameters based on the cache performance indicator is determined. The cache is dynamically resized to an optimal cache size based on a comparison of the cache performance parameters to their energy-efficient targets to reduce power consumption.
    Type: Application
    Filed: December 30, 2011
    Publication date: July 5, 2012
    Inventors: Jaideep MOSES, Rameshkumar G. Illikkal, Ravishankar Iyer, Jared E. Bendt, Sadagopan Srinivasan, Andrew J. Herdrich, Ashish V. Choubal, Avinash N. Ananthakrishnan, Vijay S.R. Degalahal
  • Methods and apparatuses for controlling thread contention
    Patent number: 8190930
    Abstract: An apparatus comprises a plurality of cores and a controller coupled to the cores. The controller is to lower an operating point of a first core if a first number based on processor clock cycles per instruction (CPI) associated with a second core is higher than a first threshold. The controller is operable to increase the operating point of the first core if the first number is lower than a second threshold.
    Type: Grant
    Filed: March 30, 2009
    Date of Patent: May 29, 2012
    Assignee: Intel Corporation
    Inventors: Andrew Herdrich, Ramesh Illikkal, Donald Newell, Ravishankar Iyer, Vineet Chadha
  • OPTIMIZED FAST HESSIAN MATRIX COMPUTATION ARCHITECTURE
    Publication number: 20120082387
    Abstract: Methods and systems of recognizing images may include an apparatus having a hardware module with logic to, for a plurality of vectors in an image, determine a first intermediate computation based on even pixels of an image vector, and determine a second intermediate computation based on odd pixels of an image vector. The logic can also combine the first and second intermediate computations into a Hessian matrix computation.
    Type: Application
    Filed: October 1, 2010
    Publication date: April 5, 2012
    Inventors: Yong Zhang, Ravishankar Iyer, Rameshkumar G. Illikkal, Donald K. Newell, Jianping Zhou
  • APPLICATION SCHEDULING IN HETEROGENEOUS MULTIPROCESSOR COMPUTING PLATFORMS
    Publication number: 20120079235
    Abstract: Methods and apparatus to schedule applications in heterogeneous multiprocessor computing platforms are described. In one embodiment, information regarding performance (e.g., execution performance and/or power consumption performance) of a plurality of processor cores of a processor is stored (and tracked) in counters and/or tables. Logic in the processor determines which processor core should execute an application based on the stored information. Other embodiments are also claimed and disclosed.
    Type: Application
    Filed: September 25, 2010
    Publication date: March 29, 2012
    Inventors: Ravishankar Iyer, Sadagopan Srinivasan, Li Zhao, Rameshkumar G. Illikkal
  • Providing application-level information for use in cache management
    Patent number: 7991956
    Abstract: In one embodiment, the present invention includes a method for associating a first identifier with data stored by a first agent in a cache line of a cache to indicate the identity of the first agent, and storing the first identifier with the data in the cache line and updating at least one of a plurality of counters associated with the first agent in a metadata storage in the cache, where the counter includes information regarding inter-agent interaction with respect to the cache line. Other embodiments are described and claimed.
    Type: Grant
    Filed: June 27, 2007
    Date of Patent: August 2, 2011
    Assignee: Intel Corporation
    Inventors: Rameshkumar Illikkal, Ravishankar Iyer, Li Zhao, Donald Newell, Carl Lebsack, Quinn A. Jacobson, Suresh Srinivas, Mingqiu Sun
  • CACHE MEMORY POWER REDUCTION TECHNIQUES
    Publication number: 20110161595
    Abstract: Methods and apparatus to provide for power consumption reduction in memories (such as cache memories) are described. In one embodiment, a virtual tag is used to determine whether to access a cache way. The virtual tag access and comparison may be performed earlier in the read pipeline than the actual tag access or comparison. In another embodiment, a speculative way hit may be used based on pre-ECC partial tag match to wake up a subset of data arrays. Other embodiments are also described.
    Type: Application
    Filed: December 26, 2009
    Publication date: June 30, 2011
    Inventors: Zhen Fang, Meenakshisundara R. Chinthamani, Li Zhao, Milind B. Kamble, Ravishankar Iyer, Seung Eun Lee, Robert S. Chappell, Ryan L. Carlson
  • Controlling Access To A Cache Memory Using Privilege Level Information
    Publication number: 20110153926
    Abstract: In one embodiment, a cache memory includes entries each to store a ring level identifier, which may indicate a privilege level of information stored in the entry. This identifier may be used in performing read accesses to the cache memory. As an example, a logic coupled to the cache memory may filter an access to one or more ways of a selected set of the cache memory based at least in part on a current privilege level of a processor and the ring level identifier of the one or more ways. Other embodiments are described and claimed.
    Type: Application
    Filed: December 23, 2009
    Publication date: June 23, 2011
    Inventors: Zhen Fang, Li Zhao, Ravishankar Iyer, Tong Li, Donald K. Newell
  • METHODS AND APPARATUSES FOR CONTROLLING CACHE OCCUPANCY RATES
    Publication number: 20110113200
    Abstract: Embodiments of an apparatus for controlling cache occupancy rates are presented. In one embodiment, an apparatus comprises a controller and monitor logic. The monitor logic determines a monitored occupancy rate associated with a first program class. The first controller regulates a first allocation probability corresponding to the first program class, based at least on the difference between a requested occupancy rate and the first monitored occupancy rate.
    Type: Application
    Filed: November 10, 2009
    Publication date: May 12, 2011
    Inventors: Jaideep Moses, Rameshkumar G. Illikkal, Donald K. Newell, Ravishankar Iyer, Kostantinos Alsopos, Li Zhao
  • Selective searching in shared cache
    Publication number: 20110113198
    Abstract: The present invention discloses a method comprising: sending request for data to a memory controller; arranging the request for data by order of importance or priority; identifying a source of the request for data; if the source is an input/output device, masking off P ways in a cache; and allocating ways in filling the cache. The method further includes extending cache allocation logic to control a tag comparison operation by using a bit to provide a hint from IO devices that certain ways will not have requested data.
    Type: Application
    Filed: November 12, 2009
    Publication date: May 12, 2011
    Inventors: Liqun Cheng, Zhen Fang, Jeffrey Wilder, Sadagopan Srinivasan, Ravishankar Iyer, Donald Newell
  • Monitoring cache usage in a distributed shared cache
    Publication number: 20110087843
    Abstract: An apparatus, method, and system are disclosed. In one embodiment the apparatus includes a cache memory, which a number of sets. Each of the sets in the cache memory have several cache lines. The apparatus also includes at least one process resource table. The process resource table maintains a cache line occupancy count of a number of cache lines. Specifically, the cache line occupancy count for each cache line describes the number of cache lines in the cache storing information utilized by a process running on a computer system. Additionally, the process resource table stores the occupancy count of less cache lines than the total number of cache lines in the cache memory.
    Type: Application
    Filed: October 9, 2009
    Publication date: April 14, 2011
    Inventors: Li Zhao, Ravishankar Iyer, Rameshkumar G. Illikkal, Erik G. Hallnor, Martin G. Dixon, Donald K. Newell
  • Cutting insert
    Patent number: D673194
    Type: Grant
    Filed: July 11, 2011
    Date of Patent: December 25, 2012
    Assignee: Kennametal Inc.
    Inventors: Jeffrey F. Kovac, Lewis Ray Morrison, Kumar Reddy Mylavaram Nikhilesh, Ravishankar Iyer