Patents by Inventor Ray Bittner
Ray Bittner has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11822899Abstract: Apparatus and methods are disclosed for performing block floating-point (BFP) operations, including in implementations of neural networks. All or a portion of one or more matrices or vectors can share one or more common exponents. Techniques are disclosed for selecting the shared common exponents. In some examples of the disclosed technology, a method includes producing BFP representations of matrices or vectors, at least two elements of the respective matrices or vectors sharing a common exponent, performing a mathematical operation on two or more of the plurality of matrices or vectors, and producing an output matrix or vector. Based on the output matrix or vector, one or more updated common exponents are selected, and an updated matrix or vector is produced having some elements that share the updated common exponents.Type: GrantFiled: November 20, 2019Date of Patent: November 21, 2023Assignee: Microsoft Technology Licensing, LLCInventors: Ray Bittner, Alessandro Forin
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Patent number: 11707059Abstract: A tree stand includes a ladder portion having first and second rails, a tree-engaging member configured to engage a tree, and a mechanism being selectively variable in length operatively interconnecting the member and the first and second rails and controlling the distance between the member and the first and second rails. A platform is pivotably connected to the first and second rails.Type: GrantFiled: January 12, 2020Date of Patent: July 25, 2023Inventor: Doran Ray Bittner
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Patent number: 11107548Abstract: Embodiments are described that leverage variability of a chip. Different areas of a chip vary in terms of reliability under a same operating condition. The variability may be captured by measuring errors over different areas of the chip. A physical factor that affects or controls the likelihood of an error on the chip can be varied. For example, the voltage supplied to a chip may be provided at different levels. At each level of the physical factor, the chip is tested for errors within the regions. Some indication of the error statistics for the regions is stored and then used to adjust power used by the chip, to adjust reliability behavior of the chip, to allow applications to control how the chip is used, to compute a signature uniquely identifying the chip, etc.Type: GrantFiled: July 10, 2020Date of Patent: August 31, 2021Assignee: Microsoft Technology Licensing, LLCInventors: Benjamin Zorn, Ray Bittner, Darko Kirovski, Karthik Pattabiraman
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Publication number: 20200342950Abstract: Embodiments are described that leverage variability of a chip. Different areas of a chip vary in terms of reliability under a same operating condition. The variability may be captured by measuring errors over different areas of the chip. A physical factor that affects or controls the likelihood of an error on the chip can be varied. For example, the voltage supplied to a chip may be provided at different levels. At each level of the physical factor, the chip is tested for errors within the regions. Some indication of the error statistics for the regions is stored and then used to adjust power used by the chip, to adjust reliability behavior of the chip, to allow applications to control how the chip is used, to compute a signature uniquely identifying the chip, etc.Type: ApplicationFiled: July 10, 2020Publication date: October 29, 2020Inventors: Benjamin Zorn, Ray Bittner, Darko Kirovski, Karthik Pattabiraman
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Patent number: 10748640Abstract: Embodiments are described that leverage variability of a chip. Different areas of a chip vary in terms of reliability under a same operating condition. The variability may be captured by measuring errors over different areas of the chip. A physical factor that affects or controls the likelihood of an error on the chip can be varied. For example, the voltage supplied to a chip may be provided at different levels. At each level of the physical factor, the chip is tested for errors within the regions. Some indication of the error statistics for the regions is stored and then used to adjust power used by the chip, to adjust reliability behavior of the chip, to allow applications to control how the chip is used, to compute a signature uniquely identifying the chip, etc.Type: GrantFiled: April 18, 2018Date of Patent: August 18, 2020Assignee: MICROSOFT TECHNOLOGY LICENSING, LLCInventors: Benjamin Zorn, Ray Bittner, Darko Kirovski, Karthik Pattabiraman
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Publication number: 20200159493Abstract: Apparatus and methods are disclosed for performing block floating-point (BFP) operations, including in implementations of neural networks. All or a portion of one or more matrices or vectors can share one or more common exponents. Techniques are disclosed for selecting the shared common exponents. In some examples of the disclosed technology, a method includes producing BFP representations of matrices or vectors, at least two elements of the respective matrices or vectors sharing a common exponent, performing a mathematical operation on two or more of the plurality of matrices or vectors, and producing an output matrix or vector. Based on the output matrix or vector, one or more updated common exponents are selected, and an updated matrix or vector is produced having some elements that share the updated common exponents.Type: ApplicationFiled: November 20, 2019Publication date: May 21, 2020Applicant: Microsoft Technology Licensing, LLCInventors: Ray Bittner, Alessandro Forin
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Publication number: 20200146278Abstract: A tree stand includes a ladder portion having first and second rails, a tree-engaging member configured to engage a tree, and a mechanism being selectively variable in length operatively interconnecting the member and the first and second rails and controlling the distance between the member and the first and second rails. A platform is pivotably connected to the first and second rails.Type: ApplicationFiled: January 12, 2020Publication date: May 14, 2020Inventor: Doran Ray Bittner
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Patent number: 10552935Abstract: A system may include a Graphics Processing Unit (GPU) and a Field Programmable Gate Array (FPGA). The system may further include a bus interface that is external to the FPGA, and that is configured to transfer data directly between the GPU and the FPGA without storing the data in a memory of a central processing unit (CPU) as an intermediary operation.Type: GrantFiled: February 5, 2018Date of Patent: February 4, 2020Assignee: Microsoft Technology Licensing, LLCInventors: Ray Bittner, Erik S. Ruf
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Patent number: 10528321Abstract: Apparatus and methods are disclosed for performing block floating-point (BFP) operations, including in implementations of neural networks. All or a portion of one or more matrices or vectors can share one or more common exponents. Techniques are disclosed for selecting the shared common exponents. In some examples of the disclosed technology, a method includes producing BFP representations of matrices or vectors, at least two elements of the respective matrices or vectors sharing a common exponent, performing a mathematical operation on two or more of the plurality of matrices or vectors, and producing an output matrix or vector. Based on the output matrix or vector, one or more updated common exponents are selected, and an updated matrix or vector is produced having some elements that share the updated common exponents.Type: GrantFiled: May 10, 2017Date of Patent: January 7, 2020Assignee: Microsoft Technology Licensing, LLCInventors: Ray Bittner, Alessandro Forin
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Publication number: 20190343109Abstract: A collapsible, portable tree stand assembly for use by hunters, outdoorsmen or a similar user for positioning the user at a suitable elevation above the ground upon the trunk of a tree or similar vertical support. The tree stand assembly includes an extension ladder having an upper and a lower ladder section, a folding frame member adapted to forcibly contact said tree at one end thereof and to be pivotally attached to the upper end of the upper ladder section, a generally planar seat member pivotally attached to the folding frame member, a generally planar foot platform pivotally attached to the upper ladder section below the upper end of the upper ladder section and a folding support strut attached at one end thereof to the foot platform and at the other end thereof to the upper end of the upper ladder section.Type: ApplicationFiled: July 19, 2019Publication date: November 14, 2019Inventor: Doran Ray Bittner
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Publication number: 20190318799Abstract: Embodiments are described that leverage variability of a chip. Different areas of a chip vary in terms of reliability under a same operating condition. The variability may be captured by measuring errors over different areas of the chip. A physical factor that affects or controls the likelihood of an error on the chip can be varied. For example, the voltage supplied to a chip may be provided at different levels. At each level of the physical factor, the chip is tested for errors within the regions. Some indication of the error statistics for the regions is stored and then used to adjust power used by the chip, to adjust reliability behavior of the chip, to allow applications to control how the chip is used, to compute a signature uniquely identifying the chip, etc.Type: ApplicationFiled: April 18, 2018Publication date: October 17, 2019Inventors: Benjamin Zorn, Ray Bittner, Darko Kirovski, Karthik Pattabiraman
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Publication number: 20190065954Abstract: In a data center, neural network evaluations can be included for services involving image or speech recognition by using a field programmable gate array (FPGA) or other parallel processor. The memory bandwidth limitations of providing weighted data sets from an external memory to the FPGA (or other parallel processor) can be managed by queuing up input data from the plurality of cores executing the services at the FPGA (or other parallel processor) in batches of at least two feature vectors. The at least two feature vectors can be at least two observation vectors from a same data stream or from different data streams. The FPGA (or other parallel processor) can then act on the batch of data for each loading of the weighted datasets.Type: ApplicationFiled: October 30, 2018Publication date: February 28, 2019Inventors: Ray A. BITTNER, JR., Frank Torsten Bernd SEIDE
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Patent number: 10140572Abstract: In a data center, neural network evaluations can be included for services involving image or speech recognition by using a field programmable gate array (FPGA) or other parallel processor. The memory bandwidth limitations of providing weighted data sets from an external memory to the FPGA (or other parallel processor) can be managed by queuing up input data from the plurality of cores executing the services at the FPGA (or other parallel processor) in batches of at least two feature vectors. The at least two feature vectors can be at least two observation vectors from a same data stream or from different data streams. The FPGA (or other parallel processor) can then act on the batch of data for each loading of the weighted datasets.Type: GrantFiled: June 25, 2015Date of Patent: November 27, 2018Assignee: Microsoft Technology Licensing, LLCInventors: Ray A. Bittner, Jr., Frank Torsten Bernd Seide
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Publication number: 20180174268Abstract: A system may include a Graphics Processing Unit (GPU) and a Field Programmable Gate Array (FPGA). The system may further include a bus interface that is external to the FPGA, and that is configured to transfer data directly between the GPU and the FPGA without storing the data in a memory of a central processing unit (CPU) as an intermediary operation.Type: ApplicationFiled: February 5, 2018Publication date: June 21, 2018Applicant: Microsoft Technology Licensing, LLCInventors: Ray Bittner, Erik S. Ruf
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Publication number: 20180157465Abstract: Apparatus and methods are disclosed for performing block floating-point (BFP) operations, including in implementations of neural networks. All or a portion of one or more matrices or vectors can share one or more common exponents. Techniques are disclosed for selecting the shared common exponents. In some examples of the disclosed technology, a method includes producing BFP representations of matrices or vectors, at least two elements of the respective matrices or vectors sharing a common exponent, performing a mathematical operation on two or more of the plurality of matrices or vectors, and producing an output matrix or vector. Based on the output matrix or vector, one or more updated common exponents are selected, and an updated matrix or vector is produced having some elements that share the updated common exponents.Type: ApplicationFiled: May 10, 2017Publication date: June 7, 2018Applicant: Microsoft Technology Licensing, LLCInventors: Ray Bittner, Alessandro Forin
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Patent number: 9978461Abstract: Embodiments are described that leverage variability of a chip. Different areas of a chip vary in terms of reliability under a same operating condition. The variability may be captured by measuring errors over different areas of the chip. A physical factor that affects or controls the likelihood of an error on the chip can be varied. For example, the voltage supplied to a chip may be provided at different levels. At each level of the physical factor, the chip is tested for errors within the regions. Some indication of the error statistics for the regions is stored and then used to adjust power used by the chip, to adjust reliability behavior of the chip, to allow applications to control how the chip is used, to compute a signature uniquely identifying the chip, etc.Type: GrantFiled: March 17, 2017Date of Patent: May 22, 2018Assignee: Microsoft Technology Licensing, LLCInventors: Benjamin Zorn, Ray Bittner, Darko Kirovski, Karthik Pattabiraman
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Patent number: 9928567Abstract: A system may include a Graphics Processing Unit (GPU) and a Field Programmable Gate Array (FPGA). The system may further include a bus interface that is external to the FPGA, and that is configured to transfer data directly between the GPU and the FPGA without storing the data in a memory of a central processing unit (CPU) as an intermediary operation.Type: GrantFiled: April 4, 2016Date of Patent: March 27, 2018Assignee: Microsoft Technology Licensing, LLCInventors: Ray Bittner, Erik S. Ruf
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Publication number: 20170323689Abstract: Embodiments are described that leverage variability of a chip. Different areas of a chip vary in terms of reliability under a same operating condition. The variability may be captured by measuring errors over different areas of the chip. A physical factor that affects or controls the likelihood of an error on the chip can be varied. For example, the voltage supplied to a chip may be provided at different levels. At each level of the physical factor, the chip is tested for errors within the regions. Some indication of the error statistics for the regions is stored and then used to adjust power used by the chip, to adjust reliability behavior of the chip, to allow applications to control how the chip is used, to compute a signature uniquely identifying the chip, etc.Type: ApplicationFiled: March 17, 2017Publication date: November 9, 2017Inventors: Benjamin Zorn, Ray Bittner, Darko Kirovski, Karthik Pattabiraman
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Patent number: 9760770Abstract: The subject disclosure is directed towards loading parallel memories (e.g., in one or more FPGAs) with multidimensional data in an interleaved manner such that a multidimensional patch/window may be filled with corresponding data in a single parallel read of the memories. Depending on the position of the patch, the data may be rotated horizontally and/or vertically, for example, so that the data in each patch is consistently arranged in the patch regardless of from which memory each piece of data was read. Also described is leveraging dual ported memory for multiple line reads and/or loading one part of a buffer while reading from another.Type: GrantFiled: June 14, 2013Date of Patent: September 12, 2017Assignee: Microsoft Technology Licensing, LLCInventors: Kenneth Hiroshi Eguro, Ray A. Bittner, Jr., George E. Smith, Shawn Michael Swilley, Rehan Ahmed
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Patent number: 9666303Abstract: Embodiments are described that leverage variability of a chip. Different areas of a chip vary in terms of reliability under a same operating condition. The variability may be captured by measuring errors over different areas of the chip. A physical factor that affects or controls the likelihood of an error on the chip can be varied. For example, the voltage supplied to a chip may be provided at different levels. At each level of the physical factor, the chip is tested for errors within the regions. Some indication of the error statistics for the regions is stored and then used to adjust power used by the chip, to adjust reliability behavior of the chip, to allow applications to control how the chip is used, to compute a signature uniquely identifying the chip, etc.Type: GrantFiled: January 23, 2015Date of Patent: May 30, 2017Assignee: Microsoft Technology Licensing, LLCInventors: Benjamin Zorn, Ray Bittner, Darko Kirovski, Karthik Pattabiraman