Abstract: In a data center, neural network evaluations can be included for services involving image or speech recognition by using a field programmable gate array (FPGA) or other parallel processor. The memory bandwidth limitations of providing weighted data sets from an external memory to the FPGA (or other parallel processor) can be managed by queuing up input data from the plurality of cores executing the services at the FPGA (or other parallel processor) in batches of at least two feature vectors. The at least two feature vectors can be at least two observation vectors from a same data stream or from different data streams. The FPGA (or other parallel processor) can then act on the batch of data for each loading of the weighted datasets.

Abstract: A system may include a Graphics Processing Unit (GPU) and a Field Programmable Gate Array (FPGA). The system may further include a bus interface that is external to the FPGA, and that is configured to transfer data directly between the GPU and the FPGA without storing the data in a memory of a central processing unit (CPU) as an intermediary operation.

Abstract: One or more techniques and/or systems are provided for creating socially authored, or community authored, summaries of documents and/or for navigating a forum comprising such summaries. In one embodiment, at least some of the summaries are generated automatically when a document is written and/or discovered (e.g., by a web crawler), for example. In another embodiment, the documents are created by users of the forum. A plurality of summaries of a document may be created (e.g., by different users), and users can provide feedback, such as comments or ratings, that may assist other users in identifying which summary or summaries better describe the document. Moreover, the users can navigate the forum and retrieve summaries by browsing categories (and subcategories) to identify a topic of interest and/or by performing a search based upon user inputted search term(s).

Abstract: A system may include a Graphics Processing Unit (GPU) and a Field Programmable Gate Array (FPGA). The system may further include a bus interface that is external to the FPGA, and that is configured to transfer data directly between the GPU and the FPGA without storing the data in a memory of a central processing unit (CPU) as an intermediary operation.

Abstract: One or more techniques and/or systems are provided for creating socially authored, or community authored, summaries of documents and/or for navigating a forum comprising such summaries. In one embodiment, at least some of the summaries are generated automatically when a document is written and/or discovered (e.g., by a web crawler), for example. In another embodiment, the documents are created by users of the forum. A plurality of summaries of a document may be created (e.g., by different users), and users can provide feedback, such as comments or ratings, that may assist other users in identifying which summary or summaries better describe the document. Moreover, the users can navigate the forum and retrieve summaries by browsing categories (and subcategories) to identify a topic of interest and/or by performing a search based upon user inputted search term(s).

Abstract: Embodiments are described that leverage variability of a chip. Different areas of a chip vary in terms of reliability under a same operating condition. The variability may be captured by measuring errors over different areas of the chip. A physical factor that affects or controls the likelihood of an error on the chip can be varied. For example, the voltage supplied to a chip may be provided at different levels. At each level of the physical factor, the chip is tested for errors within the regions. Some indication of the error statistics for the regions is stored and then used to adjust power used by the chip, to adjust reliability behavior of the chip, to allow applications to control how the chip is used, to compute a signature uniquely identifying the chip, etc.

Abstract: Embodiments are described that leverage variability of a chip. Different areas of a chip vary in terms of reliability under a same operating condition. The variability may be captured by measuring errors over different areas of the chip. A physical factor that affects or controls the likelihood of an error on the chip can be varied. For example, the voltage supplied to a chip may be provided at different levels. At each level of the physical factor, the chip is tested for errors within the regions. Some indication of the error statistics for the regions is stored and then used to adjust power used by the chip, to adjust reliability behavior of the chip, to allow applications to control how the chip is used, to compute a signature uniquely identifying the chip, etc.

Abstract: An intrusion detection system disclosed herein includes a detector circuit that measures a change in value of impedance of an interconnection circuitry. A decoder coupled to the detector decodes the measured value of the change in the impedance of the interconnection circuitry to determine existence of an abnormal condition. In an example implementation of the intrusion detection system, the change in the value of the impedance of the interconnection circuitry is represented by a change in the phase delay on the interconnection circuitry. An implementation of the intrusion detection circuit terminates communication using the interconnection circuitry upon detection of the abnormal condition. The intrusion detection system is further configured to interpret the abnormal condition as a communication signal to the interconnection circuitry.

Abstract: A set of population data that includes a plurality of individual population data entities is obtained. Each of the individual population data entities in the obtained set is streamed to an array of a plurality of evaluation functions. The evaluation functions are configured to evaluate each entity to determine an acceptability of the entity for a current state of a candidate centroid value associated with the evaluation function. Acceptance of input data entities is terminated after a first accepting one of the evaluation functions accepts an entity, based on the determined acceptability and on a predetermined priority ordering of acceptance. The first accepting one of the evaluation functions, in the priority ordering, incorporates population data associated with the accepted entity into an aggregator that is local to the first accepting evaluation function.

Abstract: The subject disclosure is directed towards loading parallel memories (e.g., in one or more FPGAs) with multidimensional data in an interleaved manner such that a multidimensional patch/window may be filled with corresponding data in a single parallel read of the memories. Depending on the position of the patch, the data may be rotated horizontally and/or vertically, for example, so that the data in each patch is consistently arranged in the patch regardless of from which memory each piece of data was read. Also described is leveraging dual ported memory for multiple line reads and/or loading one part of a buffer while reading from another.

Abstract: A system may include a Graphics Processing Unit (GPU) and a Field Programmable Gate Array (FPGA). The system may further include a bus interface that is external to the FPGA, and that is configured to transfer data directly between the GPU and the FPGA without storing the data in a memory of a central processing unit (CPU) as an intermediary operation.

Abstract: One or more techniques and/or systems are provided for creating socially authored, or community authored, summaries of documents and/or for navigating a forum comprising such summaries. In one embodiment, at least some of the summaries are generated automatically when a document is written and/or discovered (e.g., by a web crawler), for example. In another embodiment, the documents are created by users of the forum. A plurality of summaries of a document may be created (e.g., by different users), and users can provide feedback, such as comments or ratings, that may assist other users in identifying which summary or summaries better describe the document. Moreover, the users can navigate the forum and retrieve summaries by browsing categories (and subcategories) to identify a topic of interest and/or by performing a search based upon user inputted search term(s).

Abstract: One or more techniques and/or systems are provided for creating socially authored, or community authored, summaries of documents and/or for navigating a forum comprising such summaries. In one embodiment, at least some of the summaries are generated automatically when a document is written and/or discovered (e.g., by a web crawler), for example. In another embodiment, the documents are created by users of the forum. A plurality of summaries of a document may be created (e.g., by different users), and users can provide feedback, such as comments or ratings, that may assist other users in identifying which summary or summaries better describe the document. Moreover, the users can navigate the forum and retrieve summaries by browsing categories (and subcategories) to identify a topic of interest and/or by performing a search based upon user inputted search term(s).

Abstract: Embodiments are described that leverage variability of a chip. Different areas of a chip vary in terms of reliability under a same operating condition. The variability may be captured by measuring errors over different areas of the chip. A physical factor that affects or controls the likelihood of an error on the chip can be varied. For example, the voltage supplied to a chip may be provided at different levels. At each level of the physical factor, the chip is tested for errors within the regions. Some indication of the error statistics for the regions is stored and then used to adjust power used by the chip, to adjust reliability behavior of the chip, to allow applications to control how the chip is used, to compute a signature uniquely identifying the chip, etc.

Abstract: An intrusion detection system disclosed herein includes a detector circuit that measures a change in value of impedance of an interconnection circuitry. A decoder coupled to the detector decodes the measured value of the change in the impedance of the interconnection circuitry to determine existence of an abnormal condition. In an example implementation of the intrusion detection system, the change in the value of the impedance of the interconnection circuitry is represented by a change in the phase delay on the interconnection circuitry. An implementation of the intrusion detection circuit terminates communication using the interconnection circuitry upon detection of the abnormal condition. The intrusion detection system is further configured to interpret the abnormal condition as a communication signal to the interconnection circuitry.

Abstract: A side channel communications system disclosed herein includes a receiver device with an internal circuitry where the operational speed of the internal circuitry changes in response to an external signal. When the receiver device receives an external signal, the operational speed of the internal circuitry changes. A detector detects the change in the operational speed of the internal circuitry to generate an output value, which is decoded to determine the information communicated by the external signal. In one implementation of the side channel communications system, the external transmitter communicates the external signal in the form of a temperature signal. Alternatively, the external transmitter communicates the external signal in the form of a change in the supply voltage.

Abstract: An input device includes an array of adjacent capacitive sensors arranged into rows and columns. Each capacitive sensor exhibits a capacitance characteristic when in proximity to a conductive element. A plurality of mechanical hysteresis mechanisms are each deposited on and in contact with each of the capacitive sensors and configured to be actuated by a corresponding push button. Each capacitive sensor exhibits an electrical characteristic upon actuation of the corresponding mechanical hysteresis mechanism. An insulating overlay layer positioned over the array of capacitive sensors and the plurality of mechanical hysteresis mechanisms defines each push button and defines a surface for accommodating the conductive element.

Abstract: Embodiments are described that leverage variability of a chip. Different areas of a chip vary in terms of reliability under a same operating condition. The variability may be captured by measuring errors over different areas of the chip. A physical factor that affects or controls the likelihood of an error on the chip can be varied. For example, the voltage supplied to a chip may be provided at different levels. At each level of the physical factor, the chip is tested for errors within the regions. Some indication of the error statistics for the regions is stored and then used to adjust power used by the chip, to adjust reliability behavior of the chip, to allow applications to control how the chip is used, to compute a signature uniquely identifying the chip, etc.

Abstract: One or more techniques and/or systems are provided for creating socially authored, or community authored, summaries of documents and/or for navigating a forum comprising such summaries. In one embodiment, at least some of the summaries are generated automatically when a document is written and/or discovered (e.g., by a web crawler), for example. In another embodiment, the documents are created by users of the forum. A plurality of summaries of a document may be created (e.g., by different users), and users can provide feedback, such as comments or ratings, that may assist other users in identifying which summary or summaries better describe the document. Moreover, the users can navigate the forum and retrieve summaries by browsing categories (and subcategories) to identify a topic of interest and/or by performing a search based upon user inputted search term(s).

Abstract: A multi-tasking operating system and method updates PCI address values in an extension register to ensure that various threads utilize the correct values when accessing peripheral PCI devices. When application program threads require access to a PCI device, the operating system writes the high order bits of the PCI device address to two places: (1) the extension register of the PCI host bridge to allow immediate addressing of the PCI device, and (2) separate memory locations associated with the threads. When a context switch occurs from a first thread to a second thread, the operating system retrieves the stored value from the memory location associated with the second thread and writes the value to the extension register. In this manner, when the second thread requires access to its PCI device, the proper address value is already located in the extension register.