Patents by Inventor Raymond Kong

Raymond Kong has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10661251
    Abstract: High activity metal nanoparticle catalysts, such as Pd or Pt nanoparticle catalysts, are provided. Adsorption of metal precursors such as Pd or Pt precursors onto carbon based materials such as graphene followed by solventless (or low-solvent) microwave irradiation at ambient conditions results in the formation of catalysts in which metal nanoparticles are supported on i) the surface of the carbon based materials and ii) in/on/within defects/holes in the carbon based materials.
    Type: Grant
    Filed: November 27, 2018
    Date of Patent: May 26, 2020
    Assignee: Virginia Commonwealth University
    Inventors: Stanley Eugene Gilliland, III, Bernard Frank Gupton, Caleb June Kong, Brian Raymond Clark
  • Patent number: 10651853
    Abstract: A device includes a platform implemented in programmable circuitry of the device. The platform is configured to communicate with a host data processing system. The device includes a first partial reconfiguration region implemented in the programmable circuitry and coupled to the platform. The first partial reconfiguration region is reserved for implementing user-specified circuitry. The device includes timing insulation circuitry implemented in the programmable circuitry and configured to isolate timing of signals passing between the platform and the first partial reconfiguration region.
    Type: Grant
    Filed: May 23, 2019
    Date of Patent: May 12, 2020
    Assignee: Xilinx, Inc.
    Inventors: Raymond Kong, Hao Yu
  • Patent number: 10621299
    Abstract: Providing dynamic platform support for a programmable integrated circuit (IC) can include loading a circuit design for a programmable IC, wherein the circuit design specifies a link region coupled to a first infrastructure region by first connections, and a kernel region coupled to the first infrastructure region by second connections and generating a base platform from the circuit design by removing the first infrastructure region, the kernel region, and the second connections from the circuit design and adding a wrapper that includes the first connections. A new platform can be generated from the base platform where the new platform includes the link region and, within the wrapper, a second infrastructure region coupled to the link region by the first connections.
    Type: Grant
    Filed: February 5, 2018
    Date of Patent: April 14, 2020
    Assignee: XILINX, INC.
    Inventors: Hao Yu, Raymond Kong, Brian Martin, Jun Liu, Kevin Beazley
  • Patent number: 10608641
    Abstract: Hierarchical partial reconfiguration for integrated circuits includes converting, using computer hardware, a first partial reconfiguration module of a circuit design into a first partial reconfiguration container, wherein the circuit design is placed and routed, loading, using the computer hardware, a first netlist into the first partial reconfiguration container, wherein the first netlist includes a first plurality of partial reconfiguration modules that are initially empty, and including, using the computer hardware, a further netlist within each of the first plurality of partial reconfiguration modules. Using the computer hardware, the first partial reconfiguration container is implemented with the first plurality of partial reconfiguration modules being implemented within the first partial reconfiguration container.
    Type: Grant
    Filed: July 20, 2018
    Date of Patent: March 31, 2020
    Assignee: XILINX, INC.
    Inventors: Hao Yu, Raymond Kong, Brian S. Martin, Jun Liu
  • Publication number: 20200092230
    Abstract: Examples described herein provide for an electronic circuit, such as a System-on-Chip (SoC), having a Network-on-Chip (NoC). The NoC is configurable and has capabilities to be partially reconfigured. In an example, a NoC on an integrated circuit is configured. Subsystems on the integrated circuit communicate via the NoC. The NoC is partially reconfigured. A first subset of the NoC is reconfigured during the partial reconfiguration, and a second subset of the NoC is capable of continuing to pass communications uninterruptedly during the partial reconfiguration. After the partial reconfiguration, two or more of the subsystems communicate via the first subset of the NoC.
    Type: Application
    Filed: September 17, 2018
    Publication date: March 19, 2020
    Applicant: Xilinx, Inc.
    Inventors: David P. Schultz, Ian A. Swarbrick, Jun Liu, Raymond Kong, Herve Alexanian
  • Patent number: 10558777
    Abstract: A method of implementing a partial reconfiguration in an integrated circuit device is described. The method comprises reading a netlist for a design of a circuit comprising a reconfigurable module; defining a first region of the integrated circuit device having the reconfigurable module; defining a second region that encompasses the first region; placing the reconfigurable module of the design in the first region, wherein the reconfigurable module comprises a partition pin of a plurality of available partition pins; selectively removing the partition pin; routing drivers and loads that are in the second region; and generating a partial bitstream for the reconfigurable module.
    Type: Grant
    Filed: November 22, 2017
    Date of Patent: February 11, 2020
    Assignee: Xilinx, Inc.
    Inventors: Hao Yu, Raymond Kong
  • Publication number: 20200028511
    Abstract: Hierarchical partial reconfiguration for integrated circuits includes converting, using computer hardware, a first partial reconfiguration module of a circuit design into a first partial reconfiguration container, wherein the circuit design is placed and routed, loading, using the computer hardware, a first netlist into the first partial reconfiguration container, wherein the first netlist includes a first plurality of partial reconfiguration modules that are initially empty, and including, using the computer hardware, a further netlist within each of the first plurality of partial reconfiguration modules. Using the computer hardware, the first partial reconfiguration container is implemented with the first plurality of partial reconfiguration modules being implemented within the first partial reconfiguration container.
    Type: Application
    Filed: July 20, 2018
    Publication date: January 23, 2020
    Applicant: Xilinx, Inc.
    Inventors: Hao Yu, Raymond Kong, Brian S. Martin, Jun Liu
  • Publication number: 20190206566
    Abstract: Disclosed is a monitoring and treatment support system to monitor motion symptoms of tremor, bradykinesia and/or dyskinesia. A system and method are also provided for early detection of movement disorders. Further, a system and method are provided which can accurately quantify symptoms utilizing at least one measuring device at a scheduled time as arranged by medical professionals. The timer in the digital diary will remind the elderly to take medications and/or to perform motion tests. A system and method are also provided which can compute an overall motor performance score using weighting algorithm according to the results of tremor test, finger tapping test and/or spiral drawing test. The overall motor performance score is presented using comprehensive figures to both medical professionals and the elderly as a summary report for their review. The severity of movement disorders presented in graphs is compared with the treatment plan for analysis.
    Type: Application
    Filed: December 28, 2017
    Publication date: July 4, 2019
    Inventors: Raymond Kwan LAI, Ivan Man Chim TSE, Calvin Hoi Kok CHEUNG, Timothy Kin Sang LEE, Chi Pang LAM, Sing Yee NG, Eric Sai Lok LIU, Ching Ching CHEUNG, Leung CHIU, Hon Kong CHAN, Hung Keung TSE
  • Publication number: 20190200913
    Abstract: Disclosed embodiments include a complete system and platform, and a method which allows for monitoring and supporting treatment for elderly care in clinic, home, and other normal daily environments. The system includes: (1) a pressure sensitive device for receiving force response from the elderly and convert the force response into digitalized pressure data, (2) a computing device for running a movement disorder assessment module to receive digitalized pressure data, display visual instructions and feedback, and process the digitalized pressure data for calculation of movement disorder scores, and (3) a cloud based digital diary to store, access and analyze the movement disorder scores, and generate reports on demand. The method will calculate the movement disorder scores based on the digitalized pressure data. A pressure sensitive device is also disclosed.
    Type: Application
    Filed: December 28, 2017
    Publication date: July 4, 2019
    Inventors: Raymond Kwan LAI, Ivan Man Chim TSE, Calvin Hoi Kok CHEUNG, Timothy Kin Sang LEE, Chi Pang LAM, Sing Yee NG, Eric Sai Lok LIU, Ching Ching CHEUNG, Leung CHIU, Hon Kong CHAN, Hung Keung TSE
  • Patent number: 10296699
    Abstract: Implementing a circuit design for partial reconfiguration can include routing, using a processor, a net of the circuit design that connects an endpoint within a reconfigurable module with an endpoint within static circuitry external to the reconfigurable module and forming, using the processor, a set of candidate nodes including nodes used to route the net. A node from the set of candidate nodes is determined as the partition pin for partial reconfiguration.
    Type: Grant
    Filed: March 23, 2017
    Date of Patent: May 21, 2019
    Assignee: XILINX, INC.
    Inventors: Hao Yu, Raymond Kong, Jun Liu
  • Patent number: 10031760
    Abstract: Managing an accelerator may include responsive to determining a first container including a first configuration file and a second configuration file, caching, using a host processor, the second configuration file within a local memory of the host processor. The first configuration file may be provided, using the host processor, to a device of the accelerator. Responsive to a configuration event, the host processor may provide the cached second configuration file from the local memory to the device of the accelerator.
    Type: Grant
    Filed: May 20, 2016
    Date of Patent: July 24, 2018
    Assignee: XILINX, INC.
    Inventors: Sonal Santan, Raymond Kong, Yenpang Lin, Jun Liu, Ashish Gupta, Spenser Gilliland, Brian S. Martin
  • Patent number: 8549454
    Abstract: In one embodiment, a method for propagating design constraints between a module and a module instance in a circuit design is provided. A port of the module and a port/pin of the circuit design are determined, between which constraints are to be propagated. The determination of the port/pin includes determining whether or not pin of the module instance corresponding to the port is directly connected to a top-level port of the circuit design. In response to determining that the pin is directly connected to a top-level port, the top-level port is selected as the port/pin. In response to determining that the pin is not directly connected to the top-level port, the pin is selected as the port/pin. Design constraints are propagated between the port and the selected port/pin. The propagated design constraints are stored in a storage device.
    Type: Grant
    Filed: July 20, 2012
    Date of Patent: October 1, 2013
    Assignee: Xilinx, Inc.
    Inventors: Raymond Kong, David A. Knol, Frederic Revenu, Dinesh K. Monga
  • Patent number: 8296690
    Abstract: A design hierarchy based on an implementation set abstraction of a user design for an integrated circuit design includes a plurality of nodes and a definition for each of the nodes in the plurality of nodes that describes the type of elements contained in each node and the hierarchy defined by each of the nodes. Each node can include at least one implementation element of the design and the at least one implementation element can be selected among the group including a set of logical elements, a set of placed elements, and a set of placed and routed elements.
    Type: Grant
    Filed: February 7, 2008
    Date of Patent: October 23, 2012
    Assignee: Xilinx, Inc.
    Inventors: Raymond Kong, Daniel J. Downs, John J. Laurence, Richard Yachyang Sun, Sankaranarayanan Srinivasen
  • Patent number: 8196083
    Abstract: In one embodiment, a method is provided for incremental routing of a circuit design having modified and unmodified signals. Critical routed signals of the partially routed circuit design are determined. For each critical routed signal, a first set of routing constraints is applied to prevent rerouting of the signal. The partially routed circuit design is routed according to the first set of routing constraints to produce a non-conflicting routing solution. In response to the non-conflicting routing solution not meeting timing requirements, the first set of routing constraints is removed and post-routing optimization processes are performed on the non-conflicting routing solution to reduce propagation delay of one or more signals.
    Type: Grant
    Filed: December 9, 2010
    Date of Patent: June 5, 2012
    Assignee: Xilinx, Inc.
    Inventor: Raymond Kong
  • Patent number: 8141010
    Abstract: A design hierarchy based on an implementation set abstraction of a user design for an integrated circuit design includes a plurality of nodes and a definition for each of the nodes in the plurality of nodes that describes the type of elements contained in each node and the hierarchy defined by each of the nodes. Each node can include at least one implementation element of the design and the at least one implementation element can be selected among the group including a set of logical elements, a set of placed elements, and a set of placed and routed elements.
    Type: Grant
    Filed: February 8, 2008
    Date of Patent: March 20, 2012
    Assignee: Xilinx, Inc.
    Inventors: Raymond Kong, Daniel J. Downs, John J. Laurence, Richard Yachyang Sun, Sankaranarayanan Srinivasan
  • Patent number: 8015535
    Abstract: A method of limiting the routing resources of an integrated circuit (IC) that are available for use when routing multi-fanout nets can include selecting a multi-fanout net comprising a source and a plurality of loads and identifying each region of the IC which does not include at least one of the plurality of loads. Each of the regions can have a defined geometry. A type of routing resource can be selected which has a physical orientation with respect to the IC that corresponds to the geometry of the regions of the IC. Each routing resource of the selected type that is located within a region of the IC which does not include at least one of the plurality of loads can be excluded from consideration when routing the multi-fanout net.
    Type: Grant
    Filed: March 18, 2008
    Date of Patent: September 6, 2011
    Assignee: XILINX, Inc.
    Inventors: Raymond Kong, Anirban Rahut
  • Patent number: 7620923
    Abstract: A method of limiting the routing resources of an integrated circuit (IC) that are available for use when routing multi-fanout nets can include selecting a multi-fanout net comprising a source and a plurality of loads and identifying each region of the IC which does not include at least one of the plurality of loads. Each of the regions can have a defined geometry. A type of routing resource can be selected which has a physical orientation with respect to the IC that corresponds to the geometry of the regions of the IC. Each routing resource of the selected type that is located within a region of the IC which does not include at least one of the plurality of loads can be excluded from consideration when routing the multi-fanout net.
    Type: Grant
    Filed: March 18, 2008
    Date of Patent: November 17, 2009
    Assignee: Xilinx, Inc.
    Inventors: Raymond Kong, Anirban Rahut
  • Patent number: 7614025
    Abstract: A method of implementing a circuit design in a target device can include identifying routing information for a circuit design that has been at least partially implemented. A plurality of empty sites of the target device within which the circuit design is to be implemented can be identified. The method also can include determining whether each of the plurality of empty sites of the target device has a routing conflict according to the routing information of the circuit design and generating a list specifying each empty site of the target device that has a routing conflict.
    Type: Grant
    Filed: April 18, 2007
    Date of Patent: November 3, 2009
    Assignee: XILINX, Inc.
    Inventors: Raymond Kong, Sandor S. Kalman
  • Patent number: 7590960
    Abstract: A method of placing circuit elements of a partitioned circuit design on a target programmable logic device (PLD) can include mapping circuit elements of the circuit design to corresponding partitions of the circuit design, selecting a circuit element of the circuit design, and selecting a candidate location within a logic boundary on the target PLD. The method also can include validating the candidate location for the selected circuit element, at least in part, according to whether the selected circuit element belongs to a same partition of the circuit design as at least one other circuit element already placed within the logic boundary. The selected circuit element can be selectively placed at the candidate location according to the validation.
    Type: Grant
    Filed: April 18, 2007
    Date of Patent: September 15, 2009
    Assignee: Xilinx, Inc.
    Inventors: Raymond Kong, Navaratnasothie Selvakkumaran, Kamal Chaudhary
  • Patent number: 7524472
    Abstract: Disclosed herein are methods, apparatus, and compositions for removing mercury gas from coal combustion emissions and the like. Disclosed herein is a gettering composition comprising an activated montmorillonite clay, a method for removing mercury from a gas stream using the gettering composition, and an apparatus for removing mercury from a gas stream.
    Type: Grant
    Filed: November 15, 2006
    Date of Patent: April 28, 2009
    Assignee: California Earth Minerals, Corp.
    Inventor: Raymond Kong