Patents by Inventor Raymond R. Horton
Raymond R. Horton has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8342385Abstract: A transfer process for bonding a solderable device to a solderable firsl substrate having a first oxidized surface comprises placing the solderable device proximate to the first substrate in a reducing chamber, where the first surface cannot be visually observed. We place a second substrate having a second oxidized surface in the chamber in a way to visually observe the second surface. Selecting the first substrate and the second substrate so that the reduction of the second surface correlates with the reduction of the first surface provides an indication of the degree of reduction of the first surface. Introducing a reducing agent into the chamber under reducing conditions reduces the surfaces which we track by irradiating and observing the second surface; evaluate any change in the second surface during irradiation and correlate the change with first surface reduction. When sufficiently reduced, we solder the first substrate to the device.Type: GrantFiled: April 18, 2011Date of Patent: January 1, 2013Assignee: International Business Machines CorporationInventors: Bing Dang, Raymond R. Horton, Robert J. Polastre
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Publication number: 20120261458Abstract: A transfer process for bonding a solderable device to a solderable first substrate having a first oxidized surface comprises placing the solderable device proximate to the first substrate in a reducing chamber, where the first surface cannot be visually observed. We place a second substrate having a second oxidized surface in the chamber in a way to visually observe the second surface. Selecting the first substrate and the second substrate so that the reduction of the second surface correlates with the reduction of the first surface provides an indication of the degree of reduction of the first surface. Introducing a reducing agent into the chamber under reducing conditions reduces the surfaces which we track by irradiating and observing the second surface; evaluate any change in the second surface during irradiation and correlate the change with first surface reduction. When sufficiently reduced, we solder the first substrate to the device.Type: ApplicationFiled: April 18, 2011Publication date: October 18, 2012Applicant: International Business Machines CorporationInventors: Bing Dang, Raymond R. Horton, Robert J. Polastre
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Patent number: 8187923Abstract: A laser release and glass chip removal process for a integrated circuit module avoiding carrier edge cracking is provided.Type: GrantFiled: July 3, 2008Date of Patent: May 29, 2012Assignee: International Business Machines CorporationInventors: Paul Stephen Andry, Leena Paivikki Buchwalter, Matthew J. Farinelli, Sherif A. Goma, Raymond R. Horton, Edmund J. Sprogis
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Publication number: 20120091585Abstract: A laser release and glass chip removal process for a integrated circuit module avoiding carrier edge cracking is provided.Type: ApplicationFiled: December 6, 2011Publication date: April 19, 2012Applicant: International Business Machines CorporationInventors: Leena P. Buchwalter, Paul S. Andry, Matthew J. Farinelli, Sherif A. Goma, Raymond R. Horton, Edmund J. Sprogis
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Patent number: 7791168Abstract: Techniques for electronic device fabrication are provided. In one aspect, an electronic device is provided. The electronic device includes at least one interposer structure having one or more vias and a plurality of decoupling capacitors integrated therein, the at least one interposer structure being configured to allow for one or more of the plurality of decoupling capacitors to be selectively deactivated. In another aspect, a method of fabricating an electronic device including at least one interposer structure having one or more vias and a plurality of decoupling capacitors integrated therein includes the following step. One or more of the plurality of decoupling capacitors are selectively deactivated.Type: GrantFiled: October 31, 2007Date of Patent: September 7, 2010Assignee: International Business Machines CorporationInventors: Raymond R. Horton, John U. Knickerbocker, Edmund J. Sprogis, Cornelia K. Tsang
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Patent number: 7741231Abstract: Techniques for electronic device fabrication are provided. In one aspect, an electronic device is provided. The electronic device comprises at least one interposer structure having one or mole vias and a plurality of decoupling capacitors integrated therein, the at least one interposer structure being configured to allow for one or more of the plurality of decoupling capacitors to be selectively deactivated. In another aspect, a method of fabricating an electronic device comprising at least one interposer structure having one or more vias and a plurality of decoupling capacitors integrated therein comprises the following step. One or more of the plurality of decoupling capacitors are selectively deactivated.Type: GrantFiled: March 27, 2008Date of Patent: June 22, 2010Assignee: International Business Machines CorporationInventors: Raymond R. Horton, John U. Knickerbocker, Edmund J. Sprogis, Cornelia K. Tsang
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Patent number: 7691669Abstract: Techniques for electronic device fabrication are provided. In one aspect, an electronic device is provided. The electronic device comprises at least one interposer structure having one or more vias and a plurality of decoupling capacitors integrated therein, the at least one interposer structure being configured to allow for one or more of the plurality of decoupling capacitors to be selectively deactivated. In another aspect, a method of fabricating an electronic device comprising at least one interposer structure having one or more vias and a plurality of decoupling capacitors integrated therein comprises the following step. One or more of the plurality of decoupling capacitors are selectively deactivated.Type: GrantFiled: March 27, 2008Date of Patent: April 6, 2010Assignee: International Business Machines CorporationInventors: Raymond R. Horton, John U. Knickerbocker, Edmund J. Sprogis, Cornelia K. Tsang
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Patent number: 7615405Abstract: An electronic dive and method of fabricating an electronic device. The method including placing a placement guide over a top surface of a module substrate, the placement guide having a guide opening, the guide opening extending from a top surface of the placement guide to a bottom surface of the placement guide; aligning the placement guide to an integrated circuit chip position on the module substrate; fixing the placement guide to the module substrate; placing an integrated circuit chip in the guide opening, sidewalls of the placement guide opening constraining electrically conductive bonding structures on bottom surface of the integrated circuit chip to self-align to an electrically conductive module substrate contact pad on the top surface of the module substrate in the integrated circuit chip position; and bonding the bonding structures to the module substrate contact pads, the bonding structures and the module substrate contact pads in direct physical and electrical contact after the bonding.Type: GrantFiled: October 15, 2007Date of Patent: November 10, 2009Assignee: International Business Machines CorporationInventors: Paul Stephen Andry, Leena Paivikki Buchwalter, Raymond R. Horton, John Ulrich Knickerbocker, Cornelia K. Tsang, Steven Lorenz Wright
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Patent number: 7488624Abstract: Techniques for electronic device fabrication are provided. In one aspect, an electronic device is provided. The electronic device comprises at least one interposer structure having one or more vias and a plurality of decoupling capacitors integrated therein, the at least one interposer structure being configured to allow for one or more of the plurality of decoupling capacitors to be selectively deactivated. In another aspect, a method of fabricating an electronic device comprising at least one interposer structure having one or more vias and a plurality of decoupling capacitors integrated therein comprises the following step. One or more of the plurality of decoupling capacitors are selectively deactivated.Type: GrantFiled: March 27, 2008Date of Patent: February 10, 2009Assignee: International Business Machines CorporationInventors: Raymond R. Horton, John U. Knickerbocker, Edmund J. Sprogis, Cornelia K. Tsang
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Publication number: 20090032920Abstract: A laser release and glass chip removal process for a integrated circuit module avoiding carrier edge cracking is provided.Type: ApplicationFiled: July 3, 2008Publication date: February 5, 2009Applicant: International Business Machines CorporationInventors: Leena P. Buchwalter, Paul S. Andry, Matthew J. Farinelli, Sherif A. Goma, Raymond R. Horton, Edmund J. Sprogis
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Patent number: 7449067Abstract: A method for filling vias, and in particular initially blind vias, in a wafer, and various apparatus for performing the method, comprising evacuating air from the vias; trapping at least a portion of the wafer and a paste for filling the vias between two surfaces; and pressurizing the paste to fill the vias.Type: GrantFiled: November 3, 2003Date of Patent: November 11, 2008Assignee: International Business Machines CorporationInventors: Paul S. Andry, Jon A. Casey, Raymond R. Horton, Chiraq S. Patel, Edmund J. Sprogis, Brian R. Sundlof
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Patent number: 7435627Abstract: Techniques for electronic device fabrication are provided. In one aspect, an electronic device is provided. The electronic device comprises at least one interposer structure having one or more vias and a plurality of decoupling capacitors integrated therein, the at least one interposer structure being configured to allow for one or more of the plurality of decoupling capacitors to be selectively deactivated. In another aspect, a method of fabricating an electronic device comprising at least one interposer structure having one or more vias and a plurality of decoupling capacitors integrated therein comprises the following step. One or more of the plurality of decoupling capacitors are selectively deactivated.Type: GrantFiled: August 11, 2005Date of Patent: October 14, 2008Assignee: International Business Machines CorporationInventors: Raymond R. Horton, John U. Knickerbocker, Edmund J. Sprogis, Cornelia K. Tsang
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Publication number: 20080182359Abstract: Techniques for electronic device fabrication are provided. In one aspect, an electronic device is provided. The electronic device comprises at least one interposer structure having one or more vias and a plurality of decoupling capacitors integrated therein, the at least one interposer structure being configured to allow for one or more of the plurality of decoupling capacitors to be selectively deactivated. In another aspect, a method of fabricating an electronic device comprising at least one interposer structure having one or more vias and a plurality of decoupling capacitors integrated therein comprises the following step. One or more of the plurality of decoupling capacitors are selectively deactivated.Type: ApplicationFiled: March 27, 2008Publication date: July 31, 2008Applicant: International Business Machines CorporationInventors: Raymond R. Horton, John U. Knickerbocker, Edmund J. Sprogis, Cornelia K. Tsang
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Publication number: 20080182361Abstract: Techniques for electronic device fabrication are provided. In one aspect, an electronic device is provided. The electronic device comprises at least one interposer structure having one or more vias and a plurality of decoupling capacitors integrated therein, the at least one interposer structure being configured to allow for one or more of the plurality of decoupling capacitors to be selectively deactivated. In another aspect, a method of fabricating an electronic device comprising at least one interposer structure having one or more vias and a plurality of decoupling capacitors integrated therein comprises the following step. One or more of the plurality of decoupling capacitors are selectively deactivated.Type: ApplicationFiled: March 27, 2008Publication date: July 31, 2008Applicant: International Business Machines CorporationInventors: Raymond R. Horton, John U. Knickerbocker, Edmund J. Sprogis, Cornelia K. Tsang
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Publication number: 20080182362Abstract: An electronic dive and method of fabricating an electronic device. The method including placing a placement guide over a top surface of a module substrate, the placement guide having a guide opening, the guide opening extending from a top surface of the placement guide to a bottom surface of the placement guide; aligning the placement guide to an integrated circuit chip position on the module substrate; fixing the placement guide to the module substrate; placing an integrated circuit chip in the guide opening, sidewalls of the placement guide opening constraining electrically conductive bonding structures on bottom surface of the integrated circuit chip to self-align to an electrically conductive module substrate contact pad on the top surface of the module substrate in the integrated circuit chip position; and bonding the bonding structures to the module substrate contact pads, the bonding structures and the module substrate contact pads in direct physical and electrical contact after the bonding.Type: ApplicationFiled: October 15, 2007Publication date: July 31, 2008Inventors: Paul Stephen Andry, Leena Paivikki Buchwalter, Raymond R. Horton, John Ulrich Knickerbocker, Cornelia K. Tsang, Steven Lorenz Wright
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Publication number: 20080176411Abstract: Techniques for electronic device fabrication are provided. In one aspect, an electronic device is provided. The electronic device comprises at least one interposer structure having one or mole vias and a plurality of decoupling capacitors integrated therein, the at least one interposer structure being configured to allow for one or more of the plurality of decoupling capacitors to be selectively deactivated. In another aspect, a method of fabricating an electronic device comprising at least one interposer structure having one or more vias and a plurality of decoupling capacitors integrated therein comprises the following step. One or more of the plurality of decoupling capacitors are selectively deactivated.Type: ApplicationFiled: March 27, 2008Publication date: July 24, 2008Applicant: International Business Machines CorporationInventors: Raymond R. Horton, John U. Knickerbocker, Edmund J. Sprogis, Cornelia K. Tsang
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Patent number: 7282391Abstract: An electronic dive and method of fabricating an electronic device. The method including placing a placement guide over a top surface of a module substrate, the placement guide having a guide opening, the guide opening extending from a top surface of the placement guide to a bottom surface of the placement guide; aligning the placement guide to an integrated circuit chip position on the module substrate; fixing the placement guide to the module substrate; placing an integrated circuit chip in the guide opening, sidewalls of the placement guide opening constraining electrically conductive bonding structures on bottom surface of the integrated circuit chip to self-align to an electrically conductive module substrate contact pad on the top surface of the module substrate in the integrated circuit chip position; and bonding the bonding structures to the module substrate contact pads, the bonding structures and the module substrate contact pads in direct physical and electrical contact after the bonding.Type: GrantFiled: March 21, 2006Date of Patent: October 16, 2007Assignee: International Business Machines CorporationInventors: Paul Stephen Andry, Leena Paivikki Buchwalter, Raymond R. Horton, John Ulrich Knickerbocker, Cornelia K. Tsang, Steven Lorenz Wright
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Patent number: 7276787Abstract: A carrier structure and method for fabricating a carrier structure with through-vias each having a conductive structure with an effective coefficient of thermal expansion which is less than or closely matched to that of the substrate, and having an effective elastic modulus value which is less than or closely matches that of the substrate. The conductive structure may include concentric via fill areas having differing materials disposed concentrically therein, a core of the substrate material surrounded by an annular ring of conductive material, a core of CTE-matched non-conductive material surrounded by an annular ring of conductive material, a conductive via having an inner void with low CTE, or a full fill of a conductive composite material such as a metal-ceramic paste which has been sintered or fused.Type: GrantFiled: December 5, 2003Date of Patent: October 2, 2007Assignee: International Business Machines CorporationInventors: Daniel Charles Edelstein, Paul Stephen Andry, Leena Paivikki Buchwalter, Jon Alfred Casey, Sherif A. Goma, Raymond R. Horton, Gareth Geoffrey Hougham, Michael Wayne Lane, Xiao Hu Liu, Chirag Suryakant Patel, Edmund Juris Sprogis, Michelle Leigh Steen, Brian Richard Sundlof, Cornelia K. Tsang, George Frederick Walker
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Patent number: 7199450Abstract: Sealing a via using a soventless, low viscosity, high temperature stable polymer or a high solids content polymer solution of low viscosity, where the polymeric material is impregnated within the via at an elevated temperature. A supply chamber is introduced to administer the polymeric material at an elevated temperature, typically at a temperature high enough to liquefy the polymeric material. The polymeric material is introduced through heated supply lines under force from a pump, piston, or a vacuum held within said supply chamber.Type: GrantFiled: May 13, 2005Date of Patent: April 3, 2007Assignee: International Business Machines CorporationInventors: Jon A. Casey, Michael Berger, Leena P. Buchwalter, Donald F. Canaperi, Raymond R. Horton, Anurag Jain, Eric D. Perfecto, James A. Tornello
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Publication number: 20030092254Abstract: A process is described for forming a common input-output (I/O) site that is suitable for both wire-bond and solder bump flip chip connections, such as controlled-collapse chip connections (C4). The present invention is particularly suited to semiconductor chips that use copper as the interconnection material, in which the soft dielectrics used in manufacturing such chips are susceptible to damage due to bonding forces. The present invention reduces the risk of damage by providing site having a noble metal on the top surface of the pad, while providing a diffusion barrier to maintain the high conductivity of the metal interconnects. Process steps for forming an I/O site within a substrate are reduced by providing a method for selectively depositing metal layers in a feature formed in the substrate. Since the I/O sites of the present invention may be used for either wire-bond or solder bump connections, this provides increased flexibility for chip interconnection options, while also reducing process costs.Type: ApplicationFiled: December 18, 2002Publication date: May 15, 2003Inventors: George F. Walker, Ronald D. Goldblatt, Peter A. Gruber, Raymond R. Horton, Kevin S. Petrarca, Richard P. Volant, Tien-Jen Cheng