Abstract: In an example embodiment, an adaptive method of prefetching data blocks from an input/output device comprises predicting the address of each read operation reading a data block from the input/output device, the prediction based on the address of the immediately preceding read operation from the input/output device; tracking, for each read operation, whether each read operation reads a block data from the same address of the input/output device predicted for the read operation; and prefetching a data block for a read operation from the input/output device in accordance with the state of a state machine, the state of the state machine depending upon whether immediately preceding read operations read a data block from the same address of the input/output device predicted for the read operations.

Abstract: An averaging measurement circuit comprises a register successively storing a series of data words having a plurality of bits and providing, for each of said data words, a first output consisting of all of the plurality of bits of the data word and a second output consisting of a number of the higher order bits of the data word. A subtracter subtracts each second output of the register from a corresponding data sample and outputs the corresponding subtraction result. An adder adds each first output of the register to a corresponding subtraction result and storing the result in the register.

Abstract: An apparatus according to an embodiment of the present invention is disclosed. The apparatus includes a memory interface. The memory interface determines an access time of an original read request. The memory interface outputs a data ready signal when the access time of the original read request expires. An arbiter is coupled to the memory interface. The arbiter arbitrates access to the memory interface. A blocking unit is coupled to the memory interface. The blocking unit blocks a retry of the original read request from reaching the arbiter unit until the data ready signal is output by the memory interface. According to one embodiment of the memory controller a bus interface is coupled to the memory interface. The bus interface issues a deferred read signal to the device making the original read request upon receiving a signal from the arbiter.

Abstract: In an example embodiment, an adaptive method of prefetching data blocks from an input/output device comprises predicting the address of each read operation reading a data block from the input/output device, the prediction based on the address of the immediately preceding read operation from the input/output device; tracking, for each read operation, whether each read operation reads a block data from the same address of the input/output device predicted for the read operation; and prefetching a data block for a read operation from the input/output device in accordance with the state of a state machine, the state of the state machine depending upon whether immediately preceding read operations read a data block from the same address of the input/output device predicted for the read operations.

Abstract: In an example embodiment, an adaptive method of prefetching data blocks from an input/output device comprises predicting the address of each read operation reading a data block from the input/output device, the prediction based on the address of the immediately preceding read operation from the input/output device; tracking, for each read operation, whether each read operation reads a block data from the same address of the input/output device predicted for the read operation; and prefetching a data block for a read operation from the input/output device in accordance with the state of a state machine, the state of the state machine depending upon whether immediately preceding read operations read a data block from the same address of the input/output device predicted for the read operations.

Abstract: The memory array of a server device organizes conventional desktop memory so as to be able to perform error correction. Each one of several Rambus Direct Random Access Memory (“RDRAM™”) devices transfers one group of bits of a data word across a corresponding channel. An additional RDRAM™ device transfers data used for performing error correction, including chip kill, for on the data stored in the RDRAM™ devices.

Abstract: An apparatus according to an embodiment of the present invention is disclosed. The apparatus includes a memory interface. The memory interface determines an access time of an original read request. The memory interface outputs a data ready signal when the access time of the original read request expires. An arbiter is coupled to the memory interface. The arbiter arbitrates access to the memory interface. A blocking unit is coupled to the memory interface. The blocking unit blocks a retry of the original read request from reaching the arbiter unit until the data ready signal is output by the memory interface. According to one embodiment of the memory controller a bus interface is coupled to the memory interface. The bus interface issues a deferred read signal to the device making the original read request upon receiving a signal from the arbiter.

Abstract: The memory array of a server device organizes conventional desktop memory so as to be able to perform error correction. Each one of several Rambus Direct Random Access Memory (“RDRAM™”) devices transfers one group of bits of a data word across a corresponding channel. An additional RDRAM™ device transfers data used for performing error correction, including chip kill, for on the data stored in the RDRAM™ devices.

Abstract: An interrupt router includes a first interface. The first interface is coupled to a first interrupt delivery medium. The interrupt router includes a second interface. The second interface is coupled to a second interrupt delivery medium. The interrupt router includes an interrupt routing unit. The interrupt routing unit is coupled to the first interface and the second interface. The interrupt routing unit routes interrupts originating from the first interrupt delivery medium and the second interrupt delivery medium to a input/output (I/O) bus.

Abstract: A memory controller and method for clearing and copying memory in a computer system. The memory controller includes a register file having fields that store information that defines a first block of memory and indicates whether the first block of memory is to be cleared or copied to a first destination, and a first resource unit that clears or copies the first block of memory to the first destination as indicated by the first register file. The register file may store the starting address and length or size of the first block of memory, or a starting and ending address of the first block of memory. The name of the operation to be performed by the first resource unit may also be stored in the register file. A clearing operation may be performed by invalidating cache data that corresponds to the block of memory and writing zeros into the block of memory. A second register file and resource unit may also be provided and a second block of memory cleared or copied simultaneously with the first block of memory.

Abstract: A high speed local synchronous bus is disclosed for coupling processors within a multi-processor system such that local memory and secondary processing resources may be accessed without impacting data traffic along the bus. The local bus employs a message control method and apparatus which includes the ability to assert a WAIT signal when the processing resource is replying to a request. By asserting the WAIT signal all other operations on the bus are delayed until the transfer is complete. The use of the WAIT signal enables a device operating at a different speed from the primary processing resource to respond across the bus in a manner that is synchronized to the clock speed of the primary processing resource.

Abstract: A multiple bus system architecture and improved data transfer methods are disclosed for transferring data between a plurality of data processing resources. The bus structure of the present invention includes both a parallel and serial bus which interconnects data processing units and peripheral devices (collectively referred to as "agents") to permit the exchange of data and messages at high speed using a minimum of "handshake" events prior to the actual data transfer. Both the serial and parallel bus protocals are controlled by message control means coupled to each communicating agent. A local bus is coupled to processing agents within the system such that local memory and secondary processing resources may be accessed without impacting data traffic along the parallel bus. Direct access to resources coupled to the local bus of an agent from other bus agents is also controlled by the message control means.