Patents by Inventor Raymond W. Zeng
Raymond W. Zeng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11768603Abstract: Apparatuses and methods for performing multithread, concurrent access of different partition of a memory are disclosed herein. An example apparatus may include a non-volatile memory array comprising a plurality of partitions. Each of the plurality of partitions may include a respective plurality of memory cells. The apparatus may include a plurality of local controllers that each independently and concurrently access a respective one of the plurality of partitions to execute a respective memory access command of a plurality of memory access commands. The apparatus may include a controller to receive the plurality of memory access commands and to determine a respective target partition of the plurality of partitions for each of the plurality of memory access commands. The controller may be provide each of the plurality of memory access commands to a local controller of the plurality of local controllers associated with the respective target partition.Type: GrantFiled: May 5, 2022Date of Patent: September 26, 2023Assignee: Micron Technology, Inc.Inventors: Rajesh Sundaram, Derchang Kau, Owen W. Jungroth, Daniel Chu, Raymond W. Zeng, Shekoufeh Qawami
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Publication number: 20220415425Abstract: A read technique for both SLC (single level cell) and MLC (multi-level cell) cross-point memory can mitigate drift-related errors with minimal or no drift tracking. In one example, a read at a higher magnitude voltage is applied first, which causes the drift for cells in a lower threshold voltage state to be reset. In one example, the read at the first voltage can be a full float read to minimize disturb. A second read can then be performed at a lower voltage without the need to adjust the read voltage due to drift.Type: ApplicationFiled: June 25, 2021Publication date: December 29, 2022Inventors: Hemant P. RAO, Raymond W. ZENG, Prashant S. DAMLE, Zion S. KWOK, Kiran PANGAL, Mase J. TAUB
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Publication number: 20220261151Abstract: Apparatuses and methods for performing multithread, concurrent access of different partition of a memory are disclosed herein. An example apparatus may include a non-volatile memory array comprising a plurality of partitions. Each of the plurality of partitions may include a respective plurality of memory cells. The apparatus may further include a plurality of local controllers that are each configured to independently and concurrently access a respective one of the plurality of partitions to execute a respective memory access command of a plurality of memory access commands responsive to receiving the respective memory access command. The example apparatus may further include a controller configured to receive the plurality of memory access commands and to determine a respective target partition of the plurality of partitions for each of the plurality of memory access commands.Type: ApplicationFiled: May 5, 2022Publication date: August 18, 2022Applicant: Micron Technology, Inc.Inventors: RAJESH SUNDARAM, DERCHANG KAU, OWEN W. JUNGROTH, DANIEL CHU, RAYMOND W. ZENG, SHEKOUFEH QAWAMI
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Patent number: 11354040Abstract: Apparatuses and methods for performing multithread, concurrent access of different partition of a memory are disclosed herein. An example apparatus may include a non-volatile memory array comprising a plurality of partitions. Each of the plurality of partitions may include a respective plurality of memory cells. The apparatus may further include a plurality of local controllers that are each configured to independently and concurrently access a respective one of the plurality of partitions to execute a respective memory access command of a plurality of memory access commands responsive to receiving the respective memory access command. The example apparatus may further include a controller configured to receive the plurality of memory access commands and to determine a respective target partition of the plurality of partitions for each of the plurality of memory access commands.Type: GrantFiled: July 10, 2020Date of Patent: June 7, 2022Assignee: Micron Technology, Inc.Inventors: Rajesh Sundaram, Derchang Kau, Owen W. Jungroth, Daniel Chu, Raymond W. Zeng, Shekoufeh Qawami
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Publication number: 20200341635Abstract: Apparatuses and methods for performing multithread, concurrent access of different partition of a memory are disclosed herein. An example apparatus may include a non-volatile memory array comprising a plurality of partitions. Each of the plurality of partitions may include a respective plurality of memory cells. The apparatus may further include a plurality of local controllers that are each configured to independently and concurrently access a respective one of the plurality of partitions to execute a respective memory access command of a plurality of memory access commands responsive to receiving the respective memory access command. The example apparatus may further include a controller configured to receive the plurality of memory access commands and to determine a respective target partition of the plurality of partitions for each of the plurality of memory access commands.Type: ApplicationFiled: July 10, 2020Publication date: October 29, 2020Applicant: Micron Technology, Inc.Inventors: RAJESH SUNDARAM, DERCHANG KAU, OWEN W. JUNGROTH, DANIEL CHU, RAYMOND W. ZENG, SHEKOUFEH QAWAMI
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Patent number: 10719237Abstract: Apparatuses and methods for performing multithread, concurrent access of different partition of a memory are disclosed herein. An example apparatus may include a non-volatile memory array comprising a plurality of partitions. Each of the plurality of partitions may include a respective plurality of memory cells. The apparatus may further include a plurality of local controllers that are each configured to independently and concurrently access a respective one of the plurality of partitions to execute a respective memory access command of a plurality of memory access commands responsive to receiving the respective memory access command. The example apparatus may further include a controller configured to receive the plurality of memory access commands and to determine a respective target partition of the plurality of partitions for each of the plurality of memory access commands.Type: GrantFiled: January 11, 2016Date of Patent: July 21, 2020Assignee: Micron Technology, Inc.Inventors: Rajesh Sundaram, Derchang Kau, Owen W. Jungroth, Daniel Chu, Raymond W. Zeng, Shekoufeh Qawami
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Patent number: 10546634Abstract: The present disclosure relates to phase change memory control. An apparatus includes a memory controller. The memory controller includes a word line (WL) control module and a bit line (BL) control module. The memory controller is to determine a WL address based, at least in part, on a received memory address. The memory controller is further to determine a BL address. The apparatus further includes a parameter selection module to select a value of a control parameter based, at least in part, on at least one of the WL address and/or the BL address.Type: GrantFiled: September 24, 2018Date of Patent: January 28, 2020Assignee: Intel CorporationInventors: Raymond W. Zeng, Mase J. Taub, Kiran Pangal, Sandeep K. Guliani
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Patent number: 10325652Abstract: Technology for verifying cell programming for a phase change memory array is disclosed. In an example, a method may include sending a reset pulse to a phase change memory cell. The method may further include sensing a threshold voltage of the phase change memory cell in response to applying first and second verify voltages across the phase change memory cell, where the second verify voltage is lower than the first verify voltage. The method may also include determining whether the threshold voltage of the phase change memory cell was below the first or second verify voltages.Type: GrantFiled: August 29, 2017Date of Patent: June 18, 2019Assignee: Intel CorporationInventors: Daniel J. Chu, Raymond W. Zeng, Doyle Rivers
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Publication number: 20190096482Abstract: The present disclosure relates to phase change memory control. An apparatus includes a memory controller. The memory controller includes a word line (WL) control module and a bit line (BL) control module. The memory controller is to determine a WL address based, at least in part, on a received memory address. The memory controller is further to determine a BL address. The apparatus further includes a parameter selection module to select a value of a control parameter based, at least in part, on at least one of the WL address and/or the BL address.Type: ApplicationFiled: September 24, 2018Publication date: March 28, 2019Inventors: Raymond W. ZENG, Mase J. TAUB, Kiran PANGAL, Sandeep K. GULIANI
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Patent number: 10134468Abstract: The present disclosure relates to phase change memory control. An apparatus includes a memory controller. The memory controller includes a word line (WL) control module and a bit line (BL) control module. The memory controller is to determine a WL address based, at least in part, on a received memory address. The memory controller is further to determine a BL address. The apparatus further includes a parameter selection module to select a value of a control parameter based, at least in part, on at least one of the WL address and/or the BL address.Type: GrantFiled: March 21, 2017Date of Patent: November 20, 2018Assignee: Intel CorporationInventors: Raymond W. Zeng, Mase J. Taub, Kiran Pangal, Sandeep K. Guliani
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Publication number: 20180068720Abstract: Technology for verifying cell programming for a phase change memory array is disclosed. In an example, a method may include sending a reset pulse to a phase change memory cell. The method may further include sensing a threshold voltage of the phase change memory cell in response to applying first and second verify voltages across the phase change memory cell, where the second verify voltage is lower than the first verify voltage. The method may also include determining whether the threshold voltage of the phase change memory cell was below the first or second verify voltages.Type: ApplicationFiled: August 29, 2017Publication date: March 8, 2018Applicant: Intel CorporationInventors: Daniel J. Chu, Raymond W. Zeng, Doyle Rivers
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Patent number: 9792986Abstract: The present disclosure relates to phase change memory current. An apparatus includes a memory controller including a word line (WL) control module and a bit line (BL) control module, the memory controller is to initiate selection of a memory cell. The apparatus further includes a mitigation module to configure a first line selection logic to reduce a transient energy dissipation of the memory cell, the transient energy related to selecting the memory cell.Type: GrantFiled: May 29, 2015Date of Patent: October 17, 2017Assignee: INTEL CORPORATIONInventors: Mase J. Taub, Sandeep K. Guliani, Kiran Pangal, Raymond W. Zeng
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Patent number: 9747977Abstract: Technology for verifying cell programming for a phase change memory array is disclosed. In an example, a method may include sending a reset pulse to a phase change memory cell. The method may further include sensing a threshold voltage of the phase change memory cell in response to applying first and second verify voltages across the phase change memory cell, where the second verify voltage is lower than the first verify voltage. The method may also include determining whether the threshold voltage of the phase change memory cell was below the first or second verify voltages.Type: GrantFiled: March 14, 2013Date of Patent: August 29, 2017Assignee: INTEL CORPORATIONInventors: Daniel J. Chu, Raymond W. Zeng, Doyle Rivers
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Publication number: 20170229172Abstract: The present disclosure relates to phase change memory control. An apparatus includes a memory controller. The memory controller includes a word line (WL) control module and a bit line (BL) control module. The memory controller is to determine a WL address based, at least in part, on a received memory address. The memory controller is further to determine a BL address. The apparatus further includes a parameter selection module to select a value of a control parameter based, at least in part, on at least one of the WL address and/or the BL address.Type: ApplicationFiled: March 21, 2017Publication date: August 10, 2017Applicant: Intel CorporationInventors: RAYMOND W. ZENG, MASE J. TAUB, KIRAN PANGAL, SANDEEP K. GULIANI
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Publication number: 20170199666Abstract: Apparatuses and methods for performing multithread, concurrent access of different partition of a memory are disclosed herein. An example apparatus may include a non-volatile memory array comprising a plurality of partitions. Each of the plurality of partitions may include a respective plurality of memory cells. The apparatus may further include a plurality of local controllers that are each configured to independently and concurrently access a respective one of the plurality of partitions to execute a respective memory access command of a plurality of memory access commands responsive to receiving the respective memory access command. The example apparatus may further include a controller configured to receive the plurality of memory access commands and to determine a respective target partition of the plurality of partitions for each of the plurality of memory access commands.Type: ApplicationFiled: January 11, 2016Publication date: July 13, 2017Applicant: Micron Technology, Inc.Inventors: RAJESH SUNDARAM, DERCHANG KAU, OWEN W. JUNGROTH, DANIEL CHU, RAYMOND W. ZENG, SHEKOUFEH QAWAMI
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Patent number: 9685213Abstract: Embodiments of the present disclosure describe techniques and configurations for controlling current in a non-volatile random access memory (NVRAM) device. In an embodiment, the NVRAM device may include a plurality of memory cells coupled to a plurality of bit lines forming a bit line node with parasitic capacitance. Each memory cell may comprise a switch device with a required level of a holding current to maintain an on-state of the cell. A voltage supply circuitry and a controller may be coupled with the NVRAM device. The controller may control the circuitry to provide a current pulse that keeps a memory cell in on-state. The pulse may comprise a profile that changes over time from a set point to the holding current level, in response to a discharge of the bit line node capacitance through the memory cell after the set point is achieved. Other embodiments may be described and/or claimed.Type: GrantFiled: November 9, 2016Date of Patent: June 20, 2017Assignee: Intel CorporationInventors: Dany-Sebastien Ly-Gagnon, Kiran Pangal, Raymond W. Zeng, Mase J. Taub
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Patent number: 9601193Abstract: The present disclosure relates to phase change memory control. An apparatus includes a memory controller. The memory controller includes a word line (WL) control module and a bit line (BL) control module. The memory controller is to determine a WL address based, at least in part, on a received memory address. The memory controller is further to determine a BL address. The apparatus further includes a parameter selection module to select a value of a control parameter based, at least in part, on at least one of the WL address and/or the BL address.Type: GrantFiled: September 14, 2015Date of Patent: March 21, 2017Assignee: INTEL CORPORATIONInventors: Raymond W. Zeng, Mase J. Taub, Kiran Pangal, Sandeep K. Guliani
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Publication number: 20170076794Abstract: The present disclosure relates to phase change memory control. An apparatus includes a memory controller. The memory controller includes a word line (WL) control module and a bit line (BL) control module. The memory controller is to determine a WL address based, at least in part, on a received memory address. The memory controller is further to determine a BL address. The apparatus further includes a parameter selection module to select a value of a control parameter based, at least in part, on at least one of the WL address and/or the BL address.Type: ApplicationFiled: September 14, 2015Publication date: March 16, 2017Applicant: INTEL CORPORATIONInventors: RAYMOND W. ZENG, MASE J. TAUB, KIRAN PANGAL, SANDEEP K. GULIANI
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Publication number: 20170053698Abstract: Embodiments of the present disclosure describe techniques and configurations for controlling current in a non-volatile random access memory (NVRAM) device. In an embodiment, the NVRAM device may include a plurality of memory cells coupled to a plurality of bit lines forming a bit line node with parasitic capacitance. Each memory cell may comprise a switch device with a required level of a holding current to maintain an on-state of the cell. A voltage supply circuitry and a controller may be coupled with the NVRAM device. The controller may control the circuitry to provide a current pulse that keeps a memory cell in on-state. The pulse may comprise a profile that changes over time from a set point to the holding current level, in response to a discharge of the bit line node capacitance through the memory cell after the set point is achieved. Other embodiments may be described and/or claimed.Type: ApplicationFiled: November 9, 2016Publication date: February 23, 2017Inventors: Dany-Sebastien Ly-Gagnon, Kiran Pangal, Raymond W. Zeng, Mase J. Taub
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Patent number: 9543004Abstract: Embodiments of the present disclosure describe techniques and configurations for controlling current in a non-volatile random access memory (NVRAM) device. In an embodiment, the NVRAM device may include a plurality of memory cells coupled to a plurality of bit lines forming a bit line node with parasitic capacitance. Each memory cell may comprise a switch device with a required level of a holding current to maintain an on-state of the cell. A voltage supply circuitry and a controller may be coupled with the NVRAM device. The controller may control the circuitry to provide a current pulse that keeps a memory cell in on-state. The pulse may comprise a profile that changes over time from a set point to the holding current level, in response to a discharge of the bit line node capacitance through the memory cell after the set point is achieved. Other embodiments may be described and/or claimed.Type: GrantFiled: June 17, 2015Date of Patent: January 10, 2017Assignee: INTEL CORPORATIONInventors: Dany-Sebastien Ly-Gagnon, Kiran Pangal, Raymond W. Zeng, Mase J. Taub