Abstract: Embodiments of the present disclosure describe techniques and configurations for controlling current in a non-volatile random access memory (NVRAM) device. In an embodiment, the NVRAM device may include a plurality of memory cells coupled to a plurality of bit lines forming a bit line node with parasitic capacitance. Each memory cell may comprise a switch device with a required level of a holding current to maintain an on-state of the cell. A voltage supply circuitry and a controller may be coupled with the NVRAM device. The controller may control the circuitry to provide a current pulse that keeps a memory cell in on-state. The pulse may comprise a profile that changes over time from a set point to the holding current level, in response to a discharge of the bit line node capacitance through the memory cell after the set point is achieved. Other embodiments may be described and/or claimed.

Abstract: Embodiments of the present disclosure describe techniques and configurations for controlling current in a non-volatile random access memory (NVRAM) device. In an embodiment, the NVRAM device may include a plurality of memory cells coupled to a plurality of bit lines forming a bit line node with parasitic capacitance. Each memory cell may comprise a switch device with a required level of a holding current to maintain an on-state of the cell. A voltage supply circuitry and a controller may be coupled with the NVRAM device. The controller may control the circuitry to provide a current pulse that keeps a memory cell in on-state. The pulse may comprise a profile that changes over time from a set point to the holding current level, in response to a discharge of the bit line node capacitance through the memory cell after the set point is achieved. Other embodiments may be described and/or claimed.

Abstract: The present disclosure relates to phase change memory current. An apparatus includes a memory controller including a word line (WL) control module and a bit line (BL) control module, the memory controller is to initiate selection of a memory cell. The apparatus further includes a mitigation module to configure a first line selection logic to reduce a transient energy dissipation of the memory cell, the transient energy related to selecting the memory cell.

Abstract: An embodiment may include local row and column circuitry that are local to a memory cell of a memory device. Either the local row circuitry or the local column circuitry may be electrically isolated, at least in part, from at least one remaining portion of the memory device during the establishing of a voltage differential between the local row circuitry and the local column circuitry that is to permit the memory cell to be read during a read of the memory cell. The read may occur subsequent to the establishing of the voltage differential. Many variations, modifications, and alternatives are possible without departing from this embodiment.

Abstract: Technology for verifying cell programming for a phase change memory array is disclosed. In an example, a method may include sending a reset pulse to a phase change memory cell. The method may further include sensing a threshold voltage of the phase change memory cell in response to applying first and second verify voltages across the phase change memory cell, where the second verify voltage is lower than the first verify voltage. The method may also include determining whether the threshold voltage of the phase change memory cell was below the first or second verify voltages.

Abstract: The present disclosure relates to the fabrication of non-volatile memory devices. In at least one embodiment, a single transistor may be used to drive each address line, either a wordline or a bitline. Both an inhibit voltage and a selection voltage may be driven through these single transistor devices, which may be achieved with the introduction of odd and even designations for the address lines. In one operating embodiment, a selected address line may be driven to a selection voltage, and the address lines of the odd or even designation which is the same as the selected address line are allowed to float. The address lines of the odd or even designation with is different from the selected address lines are driven to an inhibit voltage, wherein adjacent floating address lines may act as shielding lines to the selected address line.

Abstract: Embodiments of the present disclosure describe methods, apparatus, and system configurations for tile-level snapback detection through a coupling capacitor in a phase-change memory array. Other embodiments may be described and claimed.

Abstract: An embodiment may include local row and column circuitry that are local to a memory cell of a memory device. Either the local row circuitry or the local column circuitry may be electrically isolated, at least in part, from at least one remaining portion of the memory device during the establishing of a voltage differential between the local row circuitry and the local column circuitry that is to permit the memory cell to be read during a read of the memory cell. The read may occur subsequent to the establishing of the voltage differential. Many variations, modifications, and alternatives are possible without departing from this embodiment.

Abstract: The present disclosure relates to the fabrication of non-volatile memory devices. In at least one embodiment, a single transistor may be used to drive each address line, either a wordline or a bitline. Both an inhibit voltage and a selection voltage may be driven through these single transistor devices, which may be achieved with the introduction of odd and even designations for the address lines. In one operating embodiment, a selected address line may be driven to a selection voltage, and the address lines of the odd or even designation which is the same as the selected address line are allowed to float. The address lines of the odd or even designation with is different from the selected address lines are driven to an inhibit voltage, wherein adjacent floating address lines may act as shielding lines to the selected address line.

Abstract: The present disclosure relates to the fabrication of non-volatile memory devices. In at least one embodiment, a single transistor may be used to drive each address line, either a wordline or a bitline. Both an inhibit voltage and a selection voltage may be driven through these single transistor devices, which may be achieved with the introduction of odd and even designations for the address lines. In one operating embodiment, a selected address line may be driven to a selection voltage, and the address lines of the odd or even designation which is the same as the selected address line are allowed to float. The address lines of the odd or even designation with is different from the selected address lines are driven to an inhibit voltage, wherein adjacent floating address lines may act as shielding lines to the selected address line.

Abstract: Embodiments of the present disclosure describe methods, apparatus, and system configurations for tile-level snapback detection through a coupling capacitor in a phase-change memory array. Other embodiments may be described and claimed.

Abstract: The present disclosure relates to the fabrication of non-volatile memory devices. In at least one embodiment, a single transistor may be used to drive each address line, either a wordline or a bitline. Both an inhibit voltage and a selection voltage may be driven through these single transistor devices, which may be achieved with the introduction of odd and even designations for the address lines. In one operating embodiment, a selected address line may be driven to a selection voltage, and the address lines of the odd or even designation which is the same as the selected address line are allowed to float. The address lines of the odd or even designation with is different from the selected address lines are driven to an inhibit voltage, wherein adjacent floating address lines may act as shielding lines to the selected address line.

Abstract: Some embodiments include a die having an output control circuit to interact with an output circuit to convert a source voltage into at least one output voltage. The die may also have a converter circuit to convert the output voltage into at least one additional output voltage.

Abstract: Some embodiments include a die having an output control circuit to interact with an output circuit to convert a source voltage into at least one output voltage. The die may also have a converter circuit to convert the output voltage into at least one additional output voltage.

Abstract: In one embodiment, the present invention includes a method to supply a negative voltage to at least one deselected wordline of a memory array. Further, while the negative voltage is supplied to deselected wordlines, a positive voltage may be supplied to a selected wordline. The memory array may be a flash memory incorporating multi-level cell architecture, in one embodiment.

Abstract: One or more MOS devices may be used as a bias selecting circuit to pass a bias voltage from a bias generator to a level shifting circuit.

Abstract: A charge pump control circuit may include a frequency synthesis device, a pump cell connected to the frequency synthesis device, and a feedforward circuit connected to the frequency synthesis device to selectively activate or deactivate the frequency synthesis device in response to a pump cell output signal.

Abstract: A charge pump control circuit may include a frequency synthesis device, a pump cell connected to the frequency synthesis device, and a feedforward circuit connected to the frequency synthesis device to selectively activate or deactivate the frequency synthesis device in response to a pump cell output signal.

Abstract: A method and apparatus for self initialization for charge pumps. The method of one embodiment comprises generating a pumped voltage at an output of the circuit. The pumped voltage is sent to a first switch. A determination is made as to whether the circuit is in a first power state. The first switch is activated to couple the pumped voltage to an initialization mechanism if the circuit is in said first power state. An internal pump node in the circuit is initialized to a first voltage potential. The first switch is deactivated to decouple the pumped voltage from the initialization mechanism after the internal pump node is charged to desired level.

Abstract: A method and apparatus for self initialization for charge pumps. The method of one embodiment comprises generating a pumped voltage at an output of the circuit. The pumped voltage is sent to a first switch. A determination is made as to whether the circuit is in a first power state. The first switch is activated to couple the pumped voltage to an initialization mechanism if the circuit is in said first power state. An internal pump node in the circuit is initialized to a first voltage potential. The first switch is deactivated to decouple the pumped voltage from the initialization mechanism after the internal pump node is charged to desired level.